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1. 发明授权

US06480018B2 Charge gain stress test circuit for nonvolatile memory and test method using the same 有权
公开(公告)号：US06480018B2
公开(公告)日：2002-11-12
申请号：US09973087
申请日：2001-10-10
申请人： Kyeong-Man Ra
发明人： Kyeong-Man Ra
IPC分类号： G01R3126
CPC分类号： G11C29/50 , G11C16/04 , G11C2029/5006
摘要： A charge gain stress test circuit for a nonvolatile memory and a test method using the same according to the present invention allow a maximum size of a voltage used for a stress lower than a voltage applied in a normal operation. The preferred embodiment sufficiently increases an absolute value of an applicable stress voltage by using a reference current to control a stress voltage value without burdening the peripheral circuits. The preferred embodiment optimizes a stress time, namely the test time.

2. 发明授权

US6146943A Method for fabricating nonvolatile memory device 失效
标题翻译：非易失性存储器件的制造方法
公开(公告)号：US6146943A
公开(公告)日：2000-11-14
申请号：US033670
申请日：1998-03-03
申请人： Woong-Lim Choi , Kyeong-Man Ra
发明人： Woong-Lim Choi , Kyeong-Man Ra
IPC分类号： G11C11/56 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11519 , G11C11/5621 , G11C16/0416 , H01L27/115 , H01L27/11517
摘要： A method is provided for fabricating a nonvolatile memory device having a simple stacked stricture with program gates. The method includes forming bitlines of second conductivity type along a first direction separated by a first prescribed distance in a substrate of a first conductivity type and forming first lines on the substrate along a second direction separated from one another by a second prescribed distance. The second direction is substantially perpendicular to the first direction, and the first lines include a first conductive layer on an isolating layer. A gate insulating layer is formed on the substrate and a tunneling insulating layer on the first conductive lines and a second conductive layer is formed on the entire surface. The second conductive layer, the tunneling insulating layer, and the first conductive lines are selectively removed to form second conductive lines along the first direction and program gates. A dielectric film is formed on the second conductive lines and a third conductive layer and an insulating layer are formed on the entire surface. The insulating layer, the third conductive layer, the dielectric film, and the second conductive lines are selectively removed to form word lines in the second direction and floating gates between the first conductive lines. Insulating sidewall spacers are formed on both sides of the patterned insulating layer, the word lines, the dielectric film, and the floating gates and contact holes are formed in the tunneling insulating layer. Then, program lines are formed coupled to the program gates through the contact holes.
摘要翻译：提供了一种用于制造具有与程序门的简单堆叠狭缝的非易失性存储器件的方法。该方法包括在第一导电类型的衬底中沿着与第一规定距离分开的第一方向形成第二导电类型的位线，并且沿着沿彼此分开第二规定距离的第二方向在衬底上形成第一线。第二方向基本上垂直于第一方向，并且第一线包括隔离层上的第一导电层。在基板上形成栅绝缘层，在整个表面上形成第一导线上的隧道绝缘层和第二导电层。选择性地去除第二导电层，隧道绝缘层和第一导电线，以沿着第一方向和程序栅极形成第二导电线。在第二导线上形成电介质膜，在整个表面上形成第三导电层和绝缘层。选择性地去除绝缘层，第三导电层，电介质膜和第二导电线以在第二方向上形成字线，并且在第一导线之间形成浮动栅极。在图案化绝缘层的两侧形成绝缘侧壁间隔物，在隧道绝缘层中形成字线，电介质膜，浮栅和接触孔。然后，通过接触孔将编程线形成为耦合到编程门。

3. 发明授权

US5998829A Non-volatile memory device incorporating a dual channel structure 失效
标题翻译：结合双通道结构的非易失性存储器件
公开(公告)号：US5998829A
公开(公告)日：1999-12-07
申请号：US985679
申请日：1997-12-05
申请人： Woong-Lim Choi , Kyeong-Man Ra
发明人： Woong-Lim Choi , Kyeong-Man Ra
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , H01L27/115
摘要： A non-volatile memory device and a method of fabricating the same are disclosed. The non-volatile memory device includes a semiconductor substrate having a first conductive type, a plurality of first, second and third impurity regions having a second conductive type in the substrate, a plurality of first insulating layer only on the substrate between the second and third impurity regions, a second insulating layer on the substrate except on the first insulating layer formed, a plurality of floating gate on the first and second insulating layers, a plurality of dielectric layer on the floating gate, a plurality of control gate on the dielectric layer.
摘要翻译：公开了一种非易失性存储器件及其制造方法。非易失性存储器件包括具有第一导电类型的半导体衬底，在衬底中具有第二导电类型的多个第一，第二和第三杂质区域，仅在第二和第三衬底之间的衬底上的多个第一绝缘层杂质区域，除了形成的第一绝缘层之外的基板上的第二绝缘层，在第一和第二绝缘层上的多个浮置栅极，浮置栅极上的多个电介质层，电介质层上的多个控制栅极。

4. 发明授权

US5777359A Semiconductor flash memory device and fabrication method of same 失效
标题翻译：半导体闪存器件及其制造方法
公开(公告)号：US5777359A
公开(公告)日：1998-07-07
申请号：US777384
申请日：1996-12-27
申请人： Kyeong Man Ra
发明人： Kyeong Man Ra
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/981
摘要： A semiconductor flash memory device comprises a substrate, a plurality of buried bit lines, an insulation film, a floating gate, an inter-layer insulation film, and a control gate formed on the inter-layer insulation film. The fabrication method comprises forming the patterned first insulation films on the substrate, forming the gate insulation film on the substrate and between the patterned first insulation films, depositing a first poly-silicon layer on the gate insulation film and the patterned first insulation film, forming a floating gate by etching the first poly-silicon layer, forming a second insulation film on each of the floating gate and the substrate having the buried bit lines therein, and forming a control gate on the second insulation film. The flash memory device realizes high yield rate due to the simplified fabrication steps and facilitated fabrication.
摘要翻译：一种半导体闪速存储器件，包括：衬底，多个掩埋位线，绝缘膜，浮栅，层间绝缘膜和形成在层间绝缘膜上的控制栅。制造方法包括在衬底上形成图案化的第一绝缘膜，在衬底上和图案化的第一绝缘膜之间形成栅极绝缘膜，在栅极绝缘膜和图案化的第一绝缘膜上沉积第一多晶硅层，形成通过蚀刻第一多晶硅层的浮置栅极，在其中具有埋入位线的浮置栅极和衬底的每个上形成第二绝缘膜，并在第二绝缘膜上形成控制栅极。由于简化的制造步骤和便于制造，闪存器件实现了高产率。

5. 发明授权

US06335243B1 Method of fabricating nonvolatile memory device 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US06335243B1
公开(公告)日：2002-01-01
申请号：US09016399
申请日：1998-01-30
申请人： Woong-Lim Choi , Kyeong-Man Ra
发明人： Woong-Lim Choi , Kyeong-Man Ra
IPC分类号： H01L21336
CPC分类号： H01L27/11517 , H01L27/115
摘要： A method of fabricating a nonvolatile memory device having a first conductivity type substrate, includes the steps of forming a gate insulating layer on the entire surface of the semiconductor substrate, forming a plurality of floating gate lines on the gate insulating layer, forming first sidewall spacers on both sides of each floating gate, forming a plurality of impurity regions having a second conductivity type in the substrate between the floating gate lines, forming a dielectric layer on the floating gate lines, forming a plurality of control gate lines on the dielectric layer, forming second sidewall spacers on both sides of the control gate lines, selectively etching the dielectric layer and the floating gate lines to form a plurality of floating gates, forming tunneling insulating layers on both sides of the floating gates, and forming a plurality of program lines between the impurity regions.
摘要翻译：一种制造具有第一导电类型基板的非易失性存储器件的方法包括以下步骤：在半导体衬底的整个表面上形成栅极绝缘层，在栅极绝缘层上形成多个浮置栅极线，形成第一侧壁间隔物在每个浮置栅极的两侧，在浮置栅极线之间的衬底中形成具有第二导电类型的多个杂质区，在浮置栅极线上形成电介质层，在电介质层上形成多个控制栅极线，在控制栅极线的两侧形成第二侧壁间隔物，选择性地蚀刻电介质层和浮动栅极线以形成多个浮置栅极，在浮置栅极的两侧形成隧穿绝缘层，并形成多个编程线杂质区之间。

6. 发明授权

US06278634B1 Reference memory cell initialization circuit and method 有权
标题翻译：参考存储单元初始化电路和方法
公开(公告)号：US06278634B1
公开(公告)日：2001-08-21
申请号：US09598211
申请日：2000-06-21
申请人： Kyeong Man Ra
发明人： Kyeong Man Ra
IPC分类号： G11C1606
CPC分类号： G11C16/3459 , G11C16/28 , G11C16/3454
摘要： A circuit and method for initializing a reference memory cell. The circuit comprises a first voltage source for supplying a first voltage to a drain of the reference memory cell in a programming mode of the reference memory cell, a second voltage source for supplying a second voltage to a control gate of the reference memory cell in the programming mode or a read mode of the reference memory cell, a third voltage source for supplying a third voltage to a source of the reference memory cell, a fourth voltage source for supplying a fourth voltage to the source of the reference memory cell in an erase mode of the reference memory cell, the fourth voltage being an erase voltage, a first switch selectively connected to the drain of the reference memory cell in response to a measure signal, for controlling a path for measuring the amount of external current flowing to the reference memory cell, a second switch connected to the source of the reference memory cell for connecting it to the third voltage source or the fourth voltage source in response to an erase control signal, and a current detector connected between the first voltage source and the drain of the reference memory cell, for starting the programming mode of the reference memory cell in response to a programming control signal.
摘要翻译：用于初始化参考存储单元的电路和方法。该电路包括用于在参考存储单元的编程模式中向参考存储单元的漏极提供第一电压的第一电压源，用于将第二电压提供给参考存储单元的控制栅极的第二电压源编程模式或参考存储单元的读取模式，用于向参考存储单元的源提供第三电压的第三电压源，用于以擦除方式向参考存储单元的源提供第四电压的第四电压源参考存储单元的模式，第四电压是擦除电压，第一开关响应于测量信号选择性地连接到参考存储单元的漏极，用于控制用于测量流向参考的外部电流量的路径存储单元，连接到所述参考存储单元的源极的第二开关，用于响应于所述存储单元将其连接到所述第三电压源或所述第四电压源擦除控制信号以及连接在参考存储单元的第一电压源和漏极之间的电流检测器，用于响应编程控制信号启动参考存储单元的编程模式。

7. 发明授权

US5751632A Device for and method of sensing data of multi-bit memory cell 失效
标题翻译：用于检测多位存储单元的数据的装置和方法
公开(公告)号：US5751632A
公开(公告)日：1998-05-12
申请号：US852497
申请日：1997-05-07
申请人： Woong Lim Choi , Kyeong Man Ra , Kyung Myung Hur
发明人： Woong Lim Choi , Kyeong Man Ra , Kyung Myung Hur
IPC分类号： G11C16/06 , G11C11/56 , G11C16/02 , G11C27/00 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5642 , G11C7/06
摘要： A device for and method of sensing data of a multi-bit memory cell includes a memory cell having a gate, a source and a drain, the memory cell being programmed with at least two voltage levels, a voltage generator coupled to the memory cell and providing the gate of the memory cell with a voltage, the voltage being increased linearly, a sensing amplifier coupled to the memory cell and generating a sensing signal when a drain voltage of the memory cell is lower than a reference voltage, a voltage detector coupled to the sensing amplifier and the voltage generator and detecting synchronously a gate voltage of the memory cell with the sensing signal of the sensing amplifier, andan A/D converter coupled to the voltage detector and translating the gate voltage detected in the voltage detector into a digital value.
摘要翻译：用于感测多位存储器单元的数据的装置和方法包括具有栅极，源极和漏极的存储单元，所述存储器单元被至少两个电压电平编程，耦合到存储器单元的电压发生器和向所述存储器单元的栅极提供电压，所述电压线性增加;感测放大器，耦合到所述存储单元，并且当所述存储单元的漏极电压低于参考电压时产生感测信号;电压检测器，耦合到感测放大器和电压发生器，并且同时检测存储器单元的栅极电压与感测放大器的感测信号，以及耦合到电压检测器的A / D转换器，并将在电压检测器中检测的栅极电压转换为数字值。

8. 发明授权

US06335553B1 Nonvolatile semiconductor memory and method of fabrication 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US06335553B1
公开(公告)日：2002-01-01
申请号：US09499381
申请日：2000-02-07
申请人： Kyeong Man Ra
发明人： Kyeong Man Ra
IPC分类号： H01L2976
CPC分类号： H01L27/11517 , H01L27/115
摘要： A contactless, nonvolatile metal oxide semiconductor memory device having a rectangular array of memory cells interconnected by word-lines in the row direction of the array and bit-lines in the column direction of the array. Each memory cell has a structurally asymmetrical pair of floating gate, MOS field effect transistors of the same row that share a common source region (bit line) within a semiconductor substrate. The asymmetry of the structure of the floating gates of the two transistors enables programming/reading and monitoring of the cell to be effected simultaneously. The structure of the floating gate is also responsible for a relatively large capacitive coupling between the floating gates and the control gate (word line) which lies above them. Since the floating gates essentially serve as a mask for implantation of program/read and monitor drain regions within the substrate, fabrication of the device incorporates self-aligning process steps.
摘要翻译：一种非接触非易失性金属氧化物半导体存储器件，具有通过阵列的行方向上的字线和阵列的列方向上的位线而互连的存储器单元的矩形阵列。每个存储单元具有在半导体衬底内共享公共源区（位线）的相同行的结构上非对称的一对浮置栅极MOS场效应晶体管。两个晶体管的浮置栅极的结构的不对称性使得能够同时对单元进行编程/读取和监视。浮动栅极的结构还负责浮置栅极和位于其上方的控制栅极（字线）之间的较大电容耦合。由于浮动栅极基本上用作用于植入衬底内的程序/读取和监测漏极区域的掩模，所以器件的制造包括自对准工艺步骤。

9. 发明授权

US06269022B1 Threshold voltage setting circuit for reference memory cell and method for setting threshold voltage using the same 有权
标题翻译：用于参考存储单元的阈值电压设定电路及使用其设定阈值电压的方法
公开(公告)号：US06269022B1
公开(公告)日：2001-07-31
申请号：US09472847
申请日：1999-12-28
申请人： Kyeong Man Ra
发明人： Kyeong Man Ra
IPC分类号： G11C1604
CPC分类号： G11C29/028 , G11C16/04 , G11C16/3454 , G11C29/50 , G11C29/50004 , G11C2029/5006
摘要： Threshold voltage setting circuit for a reference memory cell for immediate and accurate setting of a threshold voltage without time consumption; and a method for setting a threshold voltage using the same, the circuit including a reference memory cell having a source, a drain, a floating gate and a control gate, a first power source for applying a voltage to the drain of the reference memory cell under the control of the current detector when the reference memory cell is programmed, a second power source for supplying a voltage to the control gate of the reference memory cell when the reference memory cell is programmed or read, a third current connected to the source of the reference memory cell, a switch connected to the drain of the reference memory cell for controlling a path for external measuring of a current flowing to the reference memory cell in response to a measuring signal, and a current detector connected between the first power source and the drain of the reference memory cell for providing a stop signal to the first and second power sources to stop the programming of the reference memory cell forcibly when a current to the reference memory cell, which is monitored during the programming of the reference memory cell in response to a program signal, is the same with a reference stop current.
摘要翻译：用于参考存储单元的阈值电压设置电路，用于立即且准确地设置阈值电压而不耗时; 以及使用其设定阈值电压的方法，所述电路包括具有源极，漏极，浮置栅极和控制栅极的参考存储单元，用于向参考存储单元的漏极施加电压的第一电源在参考存储单元被编程时，在电流检测器的控制下，用于在参考存储器单元被编程或读取时向参考存储单元的控制栅极提供电压的第二电源，连接到参考存储器单元的源极的第三电流参考存储单元，连接到参考存储单元的漏极的开关，用于响应于测量信号控制用于外部测量流向参考存储单元的电流的路径;以及电流检测器，连接在第一电源和参考存储单元的漏极，用于向第一和第二电源提供停止信号，以便当电容器强制地停止参考存储器单元的编程响应于程序信号在参考存储器单元的编程期间监视的参考存储单元与参考停止电流相同。

10. 发明授权

US6087223A Method of fabricating flash memory with dissymmetrical floating gate 失效
标题翻译：用不对称浮栅制造闪速存储器的方法
公开(公告)号：US6087223A
公开(公告)日：2000-07-11
申请号：US64084
申请日：1998-04-22
申请人： Kyeong Man Ra
发明人： Kyeong Man Ra
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/981
摘要： A semiconductor flash memory device comprises a subrate, a plurality of buried bit lines, an insulation film, a floating gate, an inter-layer insulation film, and a control gate formed on the inter-layer insulation film. The fabrication method comprises forming the patterned first insulation films on the substrate, forming the gate insulation film on the substrate and between the patterned first insulation films, depositing a first poly-silicon layer on the gate insulation film and the patterned first insulation film, forming a floating gate by etching the first poly-silicon layer, forming a second insulation film on each of the floating gate and the substrate having the buried bit lines therein, and forming a control gate on the second insulation film. The flash memory device realizes high yield rate due to the simplified fabrication steps and facilitated fabrication.
摘要翻译：半导体闪速存储器件包括形成在层间绝缘膜上的子速率，多个掩埋位线，绝缘膜，浮动栅极，层间绝缘膜和控制栅极。制造方法包括在衬底上形成图案化的第一绝缘膜，在衬底上和图案化的第一绝缘膜之间形成栅极绝缘膜，在栅极绝缘膜和图案化的第一绝缘膜上沉积第一多晶硅层，形成通过蚀刻第一多晶硅层的浮置栅极，在其中具有埋入位线的浮置栅极和衬底的每个上形成第二绝缘膜，并在第二绝缘膜上形成控制栅极。由于简化的制造步骤和便于制造，闪存器件实现了高产率。

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