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1. 发明授权

US08295076B2 Variable resistance memory devices compensating for word line resistance 有权
标题翻译：补偿字线电阻的可变电阻存储器件
公开(公告)号：US08295076B2
公开(公告)日：2012-10-23
申请号：US12819341
申请日：2010-06-21
申请人： Young-Joo Jeon , Kwang-Woo Lee , Daewon Ha
发明人： Young-Joo Jeon , Kwang-Woo Lee , Daewon Ha
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C7/12 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028
摘要： Memory devices include a row decoder, a first variable resistance memory cell connected to a first bit line and connected to the row decoder by a word line and a second variable resistance memory cell connected to a second bit line and connected to the row decoder by the word line. The memory devices further include a bit line select circuit coupled to the first and second bit lines and configured to compensate for a difference in word line resistance between the row decoder and the respective first and second memory cells. In some embodiments, the bit line select circuit includes first and second transistors configured to selective respective ones of the first and second bit lines and the first and second transistors have different resistances that compensate for the difference in word line resistance.
摘要翻译：存储器件包括行解码器，连接到第一位线并通过字线连接到行解码器的第一可变电阻存储器单元和连接到第二位线的第二可变电阻存储单元，并且通过所述行译码器连接到行解码器字线。存储器件还包括位线选择电路，其耦合到第一和第二位线并且被配置为补偿行解码器与相应的第一和第二存储器单元之间的字线电阻的差异。在一些实施例中，位线选择电路包括配置为选择第一和第二位线中的相应的第一和第二晶体管的第一和第二晶体管，并且第一和第二晶体管具有补偿字线电阻差的不同电阻。

2. 发明申请

US20100321981A1 VARIABLE RESISTANCE MEMORY DEVICES COMPENSATING FOR WORD LINE RESISTANCE 有权
标题翻译：适用于线路电阻的可变电阻记忆体设备
公开(公告)号：US20100321981A1
公开(公告)日：2010-12-23
申请号：US12819341
申请日：2010-06-21
申请人： Young-Joo Jeon , Kwang-Woo Lee , Daewon Ha
发明人： Young-Joo Jeon , Kwang-Woo Lee , Daewon Ha
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C7/12 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028
摘要： Memory devices include a row decoder, a first variable resistance memory cell connected to a first bit line and connected to the row decoder by a word line and a second variable resistance memory cell connected to a second bit line and connected to the row decoder by the word line. The memory devices further include a bit line select circuit coupled to the first and second bit lines and configured to compensate for a difference in word line resistance between the row decoder and the respective first and second memory cells. In some embodiments, the bit line select circuit includes first and second transistors configured to selective respective ones of the first and second bit lines and the first and second transistors have different resistances that compensate for the difference in word line resistance.
摘要翻译：存储器件包括行解码器，连接到第一位线并通过字线连接到行解码器的第一可变电阻存储器单元和连接到第二位线的第二可变电阻存储单元，并且通过所述行译码器连接到行解码器字线。存储器件还包括位线选择电路，其耦合到第一和第二位线并且被配置为补偿行解码器与相应的第一和第二存储器单元之间的字线电阻的差异。在一些实施例中，位线选择电路包括配置为选择第一和第二位线中的相应的第一和第二晶体管的第一和第二晶体管，并且第一和第二晶体管具有补偿字线电阻差的不同电阻。

3. 发明授权

US07612360B2 Non-volatile memory devices having cell diodes 失效
标题翻译：具有单元二极管的非易失性存储器件
公开(公告)号：US07612360B2
公开(公告)日：2009-11-03
申请号：US11782682
申请日：2007-07-25
申请人： Kwang-woo Lee , Jae-hee Oh , Chang-wook Jeong
发明人： Kwang-woo Lee , Jae-hee Oh , Chang-wook Jeong
IPC分类号： H01L29/04
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： An integrated circuit memory cell includes a substrate having a first semiconductor region of first conductivity type (e.g., N-type) therein, which may define a portion of a word line within the substrate. An electrically insulating layer is provided on the substrate. The electrically insulating layer has an opening therein that extends opposite a recess in the first semiconductor region. A first insulating spacer is provided on a sidewall of the recess in the first semiconductor region. A diode is provided in the opening. The diode has a first terminal electrically coupled to a bottom of the recess in the first semiconductor region. A variable resistivity material region (e.g., phase-changeable material region) is also provided. The variable resistivity material region is electrically coupled to a second terminal of the diode.
摘要翻译：集成电路存储单元包括其中具有第一导电类型的第一半导体区域（例如，N型）的衬底，其可以限定衬底内的字线的一部分。在基板上设置电绝缘层。电绝缘层在其中具有与第一半导体区域中的凹部相对的开口。第一绝缘间隔件设置在第一半导体区域中的凹部的侧壁上。在开口中设置一个二极管。二极管具有电耦合到第一半导体区域中的凹部的底部的第一端子。还提供了可变电阻率材料区域（例如，相变材料区域）。可变电阻率材料区域电耦合到二极管的第二端子。

4. 发明授权

US08859236B2 Microorganism with improved production of 5′-xanthosine monophosphate and 5′-guanine monophosphate, and production method of 5′-xanthosine monophosphate and 5′-guanine monophosphate using same 有权
标题翻译：具有5'-黄嘌呤单磷酸和5'-鸟嘌呤一磷酸的生产的微生物，以及使用其的5'-芒硝单磷酸和5'-鸟嘌呤一磷酸的生产方法
公开(公告)号：US08859236B2
公开(公告)日：2014-10-14
申请号：US13635801
申请日：2011-03-17
申请人： Jin Man Cho , Jin Nam Lee , Hye Won Kim , Ji Hye Lee , Nan Young Yoon , Kwang Woo Lee , Yoon Seok Oh , Jang Hee Park
发明人： Jin Man Cho , Jin Nam Lee , Hye Won Kim , Ji Hye Lee , Nan Young Yoon , Kwang Woo Lee , Yoon Seok Oh , Jang Hee Park
IPC分类号： C12Q1/00 , C12Q1/26 , C12N15/77 , C12N9/26 , C12P19/32 , C12N9/06
CPC分类号： C12N15/77 , C12N9/0026 , C12P19/32 , C12Y105/99008 , Y02P20/582
摘要： The present invention relates to a microorganism with improved production of 5′-xanthosine monophosphate and 5′-guanine monophosphate, and more specifically, to a Corynebacterium sp. microorganism having increased proline dehydrogenase activity compared with an intrinsic activity thereof, a method for producing 5′-xanthosine monophosphate or 5′-guanine monophosphate from the culture medium obtained by culturing the transformed microorganism, and a use of the microorganism for production of 5′-xanthosine monophosphate or 5′-guanine monophosphate.
摘要翻译：本发明涉及一种具有5'-黄嘌呤一磷酸和5'-鸟嘌呤一磷酸的生产的微生物，更具体地说，涉及一种棒状杆菌属。与其内在活性相比具有增加的脯氨酸脱氢酶活性的微生物，从通过培养转化的微生物获得的培养基中生产5'-黄嘌呤一磷酸或5'-鸟嘌呤一磷酸的方法，以及该微生物用于生产5' 单磷酸黄烷磷酸酯或5'-鸟嘌呤单磷酸酯。

5. 发明申请

US20130095529A1 Microorganism with Improved Production of 5'-Xanthosine Monophosphate and 5'-Guanine Monophosphate, and Production Method of 5'-Xanthosine Monophosphate and 5'-Guanine Monophosphate Using Same 有权
标题翻译：具有改善的5'-芒硝单磷酸和5'-鸟嘌呤单磷酸的生产的微生物，以及使用其的5'-芒硝单磷酸和5'-鸟嘌呤一磷酸的生产方法
公开(公告)号：US20130095529A1
公开(公告)日：2013-04-18
申请号：US13635801
申请日：2011-03-17
申请人： Jin Man Cho , Jin Nam Lee , Hye Won Kim , Ji Hye Lee , Nan Young Yoon , Kwang Woo Lee , Yoon Seok Oh , Jang Hee Park
发明人： Jin Man Cho , Jin Nam Lee , Hye Won Kim , Ji Hye Lee , Nan Young Yoon , Kwang Woo Lee , Yoon Seok Oh , Jang Hee Park
IPC分类号： C12N15/77
CPC分类号： C12N15/77 , C12N9/0026 , C12P19/32 , C12Y105/99008 , Y02P20/582
摘要： The present invention relates to a microorganism with improved production of 5′-xanthosine monophosphate and 5′-guanine monophosphate, and more specifically, to a Corynebacterium sp. microorganism having increased proline dehydrogenase activity compared with an intrinsic activity thereof, a method for producing 5′-xanthosine monophosphate or 5′-guanine monophosphate from the culture medium obtained by culturing the transformed microorganism, and a use of the microorganism for production of 5′-xanthosine monophosphate or 5′-guanine monophosphate.
摘要翻译：本发明涉及一种具有5'-黄嘌呤一磷酸和5'-鸟嘌呤一磷酸的生产的微生物，更具体地说，涉及一种棒状杆菌属。与其内在活性相比具有增加的脯氨酸脱氢酶活性的微生物，从通过培养转化的微生物获得的培养基中生产5'-黄嘌呤一磷酸或5'-鸟嘌呤一磷酸的方法，以及该微生物用于生产5' 单磷酸黄烷磷酸酯或5'-鸟嘌呤单磷酸酯。

6. 发明授权

US08102729B2 Resistive memory device capable of compensating for variations of bit line resistances 有权
标题翻译：能够补偿位线电阻变化的电阻式存储器件
公开(公告)号：US08102729B2
公开(公告)日：2012-01-24
申请号：US12659689
申请日：2010-03-17
申请人： Jung Hyuk Lee , Daewon Ha , Kwang-Woo Lee
发明人： Jung Hyuk Lee , Daewon Ha , Kwang-Woo Lee
IPC分类号： G11C8/08
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028 , G11C2213/72
摘要： A variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines.
摘要翻译：可变电阻存储器件可以包括分别连接到不同长度的位线的第一和第二存储器单元，以及选择电路，其被配置为选择通过字线连接到第一和第二存储器单元的第一和第二存储器单元。选择电路被配置为补偿位线的不同长度中的电阻差。

7. 发明申请

US20100271867A1 Variable resistive memory device compensating bit line resistance 有权
标题翻译：可变电阻存储器件补偿位线电阻
公开(公告)号：US20100271867A1
公开(公告)日：2010-10-28
申请号：US12659689
申请日：2010-03-17
申请人： Jung Hyuk Lee , Daewon Ha , Kwang-Woo Lee
发明人： Jung Hyuk Lee , Daewon Ha , Kwang-Woo Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028 , G11C2213/72
摘要： Provided is a variable resistance memory device. The variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells through word lines. The select circuit is configured to compensate for a difference of resistances in the different of the lengths of the bit lines.
摘要翻译：提供了可变电阻存储器件。可变电阻存储器件可以包括分别连接到不同长度的位线的第一和第二存储器单元，以及选择电路，其被配置为选择通过字线连接到第一和第二存储器单元的第一和第二存储器单元。选择电路被配置为补偿位线的不同长度中的电阻差。

8. 发明申请

US20080203455A1 SEMICONDUCTOR DEVICE EMPLOYING TRANSISTOR HAVING RECESSED CHANNEL REGION AND METHOD OF FABRICATING THE SAME 有权
标题翻译：使用带有通道区域的半导体器件及其制造方法
公开(公告)号：US20080203455A1
公开(公告)日：2008-08-28
申请号：US12034482
申请日：2008-02-20
申请人： Sung-Ho JANG , Yong-Jin CHOI , Min-Sung KANG , Kwang-Woo LEE
发明人： Sung-Ho JANG , Yong-Jin CHOI , Min-Sung KANG , Kwang-Woo LEE
IPC分类号： H01L27/108 , H01L21/28
CPC分类号： H01L29/66553 , H01L27/10814 , H01L27/10876 , H01L29/4236 , H01L29/42376 , H01L29/66621
摘要： A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the active region, a lower trench region and a buffer trench region interposed between the upper trench region and the lower trench region. A width of the lower trench region may be greater than a width of the upper trench region. An inner wall of the trench structure may include a convex region interposed between the upper trench region and the buffer trench region and another convex region interposed between the buffer trench region and the lower trench region. A gate electrode is disposed in the trench structure. A gate dielectric layer is interposed between the gate electrode and the trench structure.
摘要翻译：公开了采用具有凹陷沟道区的晶体管的半导体器件及其制造方法。半导体衬底具有有源区。沟槽结构被限定在有源区域内。沟槽结构包括与有源区的表面相邻的上沟槽区，下沟槽区和介于上沟槽区和下沟槽区之间的缓冲沟槽区。下沟槽区域的宽度可以大于上沟槽区域的宽度。沟槽结构的内壁可以包括插入在上沟槽区域和缓冲沟槽区域之间的凸起区域和插入在缓冲沟槽区域和下部沟槽区域之间的另一个凸起区域。栅电极设置在沟槽结构中。栅电介质层介于栅电极和沟槽结构之间。

9. 发明授权

US08299517B2 Semiconductor device employing transistor having recessed channel region and method of fabricating the same 有权
标题翻译：采用具有凹陷沟道区域的晶体管的半导体器件及其制造方法
公开(公告)号：US08299517B2
公开(公告)日：2012-10-30
申请号：US12034482
申请日：2008-02-20
申请人： Sung-Ho Jang , Yong-Jin Choi , Min-Sung Kang , Kwang-Woo Lee
发明人： Sung-Ho Jang , Yong-Jin Choi , Min-Sung Kang , Kwang-Woo Lee
IPC分类号： H01L27/108
CPC分类号： H01L29/66553 , H01L27/10814 , H01L27/10876 , H01L29/4236 , H01L29/42376 , H01L29/66621
摘要： A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the active region, a lower trench region and a buffer trench region interposed between the upper trench region and the lower trench region. A width of the lower trench region may be greater than a width of the upper trench region. An inner wall of the trench structure may include a convex region interposed between the upper trench region and the buffer trench region and another convex region interposed between the buffer trench region and the lower trench region. A gate electrode is disposed in the trench structure. A gate dielectric layer is interposed between the gate electrode and the trench structure.
摘要翻译：公开了采用具有凹陷沟道区的晶体管的半导体器件及其制造方法。半导体衬底具有有源区。沟槽结构被限定在有源区域内。沟槽结构包括与有源区的表面相邻的上沟槽区，下沟槽区和介于上沟槽区和下沟槽区之间的缓冲沟槽区。下沟槽区域的宽度可以大于上沟槽区域的宽度。沟槽结构的内壁可以包括插入在上沟槽区域和缓冲沟槽区域之间的凸起区域和插入在缓冲沟槽区域和下部沟槽区域之间的另一个凸起区域。栅电极设置在沟槽结构中。栅电介质层介于栅电极和沟槽结构之间。

10. 发明申请

US20080280390A1 METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE HAVING SELF-ALIGNED ELECTRODE, RELATED DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME 审中-公开
标题翻译：具有自对准电极的半导体存储器件的制造方法，相关器件及其相关的电子系统
公开(公告)号：US20080280390A1
公开(公告)日：2008-11-13
申请号：US12045612
申请日：2008-03-10
申请人： Jung-In KIM , Jae-Hee OH , Jun-Hyok KONG , Jae-Hyun PARK , Kwang-Woo LEE
发明人： Jung-In KIM , Jae-Hee OH , Jun-Hyok KONG , Jae-Hyun PARK , Kwang-Woo LEE
IPC分类号： H01L47/00
CPC分类号： H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/141 , H01L45/1683
摘要： A method of fabricating a semiconductor memory device having a self-aligned electrode is provided. An interlayer insulating layer having a contact hole is formed on a substrate. A phase change pattern partially filling the contact hole is formed. A bit line which includes a bit extension self-aligned to the phase change pattern and crosses over the interlayer insulating layer is formed. The bit extension may extend in the contact hole on the phase change pattern. The bit extension contacts the phase change pattern.
摘要翻译：提供了一种制造具有自对准电极的半导体存储器件的方法。在基板上形成具有接触孔的层间绝缘层。形成部分填充接触孔的相变图案。形成了包括与相变图案自对准并与层间绝缘层交叉的位扩展的位线。钻头延伸部可以在相变图案上的接触孔中延伸。位扩展接触相变模式。

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