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1. 发明授权

US08335883B2 Data processing device and data processing system 有权
标题翻译：数据处理装置和数据处理系统
公开(公告)号：US08335883B2
公开(公告)日：2012-12-18
申请号：US12854284
申请日：2010-08-11
申请人： Shohei Tateyama , Takao Yamauchi , Eisaku Tomida , Kunihiko Nishiyama , Yasuyuki Suzuki
发明人： Shohei Tateyama , Takao Yamauchi , Eisaku Tomida , Kunihiko Nishiyama , Yasuyuki Suzuki
IPC分类号： G06F13/36 , G06F13/28
CPC分类号： G06F13/385
摘要： To provide a data processing device in which a plurality of CPUs can individually and independently communicate with different functions of a USB device using a single communication path. The data processing device is configured so that a USB host module to be coupled to a plurality of central processing units has a plurality of pipes to communicate with an arbitrary end point of a USB device coupled from the outside of the data processing device, the data processing device also includes an access control register to specify which central processing unit should have a right to control the pipe and specify to which extent a range of the content of setting of a function for the pipe should be allowed, and a USB host interface is controlled in accordance with the content of setting of the access control register.
摘要翻译：为了提供一种数据处理装置，其中多个CPU可以使用单个通信路径独立且独立地与USB设备的不同功能通信。数据处理装置被配置为使得要耦合到多个中央处理单元的USB主机模块具有多个管道以与从数据处理设备的外部耦合的USB设备的任意端点进行通信，数据处理装置还包括访问控制寄存器，以指定哪个中央处理单元应当具有控制管道的权利，并且指定应该允许管道功能的设置内容的范围在哪个范围内，并且USB主机接口是根据访问控制寄存器的设置内容进行控制。

2. 发明授权

US07774017B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07774017B2
公开(公告)日：2010-08-10
申请号：US11586671
申请日：2006-10-26
申请人： Takahiro Irita , Kunihiko Nishiyama , Saneaki Tamaki , Takao Koike , Koji Goto , Masayuki Ito
发明人： Takahiro Irita , Kunihiko Nishiyama , Saneaki Tamaki , Takao Koike , Koji Goto , Masayuki Ito
IPC分类号： H04M1/00
CPC分类号： H04B1/40
摘要： A processing load of a high performance application processing such as a voice, an image and the like is reduced, and a processing capacity of a base band processing is improved. A semiconductor integrated circuit device used in a mobile communication system such as a cellular phone is provided with a base band CPU block performing a base band processing for executing a base band protocol stack, an application system CPU block executing a high-level OS and controlling applications other than the base band processing, an application real-time CPU block executing a real-time OS and the like and controlling an image/voice processing, all of which are formed on one semiconductor chip. Further, internal high-speed buses to which these CPU blocks are connected are respectively connected via bridges.
摘要翻译：降低诸如语音，图像等的高性能应用处理的处理负担，并提高基带处理的处理能力。在诸如蜂窝电话的移动通信系统中使用的半导体集成电路装置设置有执行基带协议栈的基带处理的基带CPU块，执行高级OS的应用系统CPU块和控制除了基带处理之外的应用，执行实时OS等的应用实时CPU块和控制图像/语音处理，所有这些都形成在一个半导体芯片上。此外，连接这些CPU块的内部高速总线分别通过桥连接。

3. 发明申请

US20070098046A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070098046A1
公开(公告)日：2007-05-03
申请号：US11586671
申请日：2006-10-26
申请人： Takahiro Irita , Kunihiko Nishiyama , Saneaki Tamaki , Takao Koike , Koji Goto , Masayuki Ito
发明人： Takahiro Irita , Kunihiko Nishiyama , Saneaki Tamaki , Takao Koike , Koji Goto , Masayuki Ito
IPC分类号： H04B1/00
CPC分类号： H04B1/40
摘要： A processing load of a high performance application processing such as a voice, an image and the like is reduced, and a processing capacity of a base band processing is improved. A semiconductor integrated circuit device used in a mobile communication system such as a cellular phone is provided with a base band CPU block performing a base band processing for executing a base band protocol stack, an application system CPU block executing a high-level OS and controlling applications other than the base band processing, an application real-time CPU block executing a real-time OS and the like and controlling an image/voice processing, all of which are formed on one semiconductor chip. Further, internal high-speed buses to which these CPU blocks are connected are respectively connected via bridges.
摘要翻译：降低诸如语音，图像等的高性能应用处理的处理负担，并提高基带处理的处理能力。在诸如蜂窝电话的移动通信系统中使用的半导体集成电路装置设置有执行基带协议栈的基带处理的基带CPU块，执行高级OS的应用系统CPU块和控制除了基带处理之外的应用，执行实时OS等的应用实时CPU块和控制图像/语音处理，所有这些都形成在一个半导体芯片上。此外，连接这些CPU块的内部高速总线分别通过桥连接。

4. 发明申请

US20070112993A1 Data processor 审中-公开
标题翻译：数据处理器
公开(公告)号：US20070112993A1
公开(公告)日：2007-05-17
申请号：US11651495
申请日：2007-01-10
申请人： Tadashi Teranuma , Hironobu Hasegawa , Kunihiko Nishiyama , Yoshihiko Tsuchihashi
发明人： Tadashi Teranuma , Hironobu Hasegawa , Kunihiko Nishiyama , Yoshihiko Tsuchihashi
IPC分类号： G06F13/36
CPC分类号： G06F13/4036
摘要： A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus bridge circuit connecting the first and second buses. The bus bridge circuit has a first transfer controller, responsive to an access request from the first bus to the second bus, for obtaining a bus right of the second bus, and a second transfer controller, responsive to an access request from the second bus to the first bus, for obtaining a bus right of the first bus. The second bus has a first path connecting the second bus slave module and the first transfer controller and a second path connecting the second bus master module and the second transfer controller.
摘要翻译：数据处理器具有连接到第一总线的第一总线主模块，第一总线从模块和第一总线右仲裁电路，第二总线主模块，第二总线从模块和连接到第二总线的第二总线右仲裁电路，以及连接第一和第二巴士的公交桥电路。总线桥电路具有第一传输控制器，响应于从第一总线到第二总线的访问请求，用于获得第二总线的总线权限，以及第二传输控制器，响应于来自第二总线的访问请求第一辆公共汽车，用于获得第一辆公共汽车的公交车。第二总线具有连接第二总线从属模块和第一传输控制器的第一路径以及连接第二总线主模块和第二传输控制器的第二路径。

5. 发明申请

US20050273538A1 Data processor 有权
标题翻译：数据处理器
公开(公告)号：US20050273538A1
公开(公告)日：2005-12-08
申请号：US11142258
申请日：2005-06-02
申请人： Tadashi Teranuma , Hironobu Hasegawa , Kunihiko Nishiyama , Yoshihiko Tsuchihashi
发明人： Tadashi Teranuma , Hironobu Hasegawa , Kunihiko Nishiyama , Yoshihiko Tsuchihashi
IPC分类号： G06F13/36 , G06F13/00 , G06F13/40 , G06F15/78
CPC分类号： G06F13/4036
摘要： A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus bridge circuit connecting the first and second buses. The bus bridge circuit has a first transfer controller, responsive to an access request from the first bus to the second bus, for obtaining a bus right of the second bus, and a second transfer controller, responsive to an access request from the second bus to the first bus, for obtaining a bus right of the first bus. The second bus has a first path connecting the second bus slave module and the first transfer controller and a second path connecting the second bus master module and the second transfer controller.
摘要翻译：数据处理器具有连接到第一总线的第一总线主模块，第一总线从模块和第一总线右仲裁电路，第二总线主模块，第二总线从模块和连接到第二总线的第二总线右仲裁电路，以及连接第一和第二巴士的公交桥电路。总线桥电路具有第一传输控制器，响应于从第一总线到第二总线的访问请求，用于获得第二总线的总线权限，以及第二传输控制器，响应于来自第二总线的访问请求第一辆公共汽车，用于获得第一辆公共汽车的公交车。第二总线具有连接第二总线从属模块和第一传输控制器的第一路径以及连接第二总线主模块和第二传输控制器的第二路径。

6. 发明申请

US20130073831A1 SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM HAVING A REDUCED NUMBER OF TERMINALS ALLOCATED FOR EXTERNALLY ACCESSED ADDRESS 有权
标题翻译：具有分配给外部接入地址的终端数量减少的半导体器件和数据处理系统
公开(公告)号：US20130073831A1
公开(公告)日：2013-03-21
申请号：US13618369
申请日：2012-09-14
申请人： Masaaki Hirano , Kunihiko Nishiyama
发明人： Masaaki Hirano , Kunihiko Nishiyama
IPC分类号： G06F12/00
CPC分类号： G06F13/385 , G06F12/02
摘要： There is provided a semiconductor device having a reduced number of external terminals allocated for address input to receive access from outside, while realizing a high-speed response to an access from outside. The semiconductor device employs, in order to allow other external devices to directly access resources it possesses in its own address space, in an external interface circuit, external terminals which input a part of the address signal required for access from outside, a supplementary register which supplements the upper portion of address information that has been input from the external terminals, a mode register accessible from outside, and an address control circuit which generates an address signal to access the address space in a form based on information input from the external terminals, required supplementary information, and mode information of the mode register.
摘要翻译：提供了一种半导体器件，其具有减少的用于地址输入的外部端子数量以从外部接收访问的外部端子，同时实现对来自外部的访问的高速响应。半导体器件为了允许其他外部设备在其自己的地址空间中直接访问其外部接口电路中的资源，输入外部接入所需的部分地址信号的外部端子，附加寄存器补充从外部端子输入的地址信息的上部，可从外部访问的模式寄存器，以及地址控制电路，其基于从外部端子输入的信息，生成以形式访问地址空间的地址信号，所需的补充信息和模式寄存器的模式信息。

7. 发明授权

US08543735B2 Semiconductor device and data processing system having reduced number of terminals allocated for externally accessed address 有权
标题翻译：具有分配给外部访问地址的终端数量减少的半导体器件和数据处理系统
公开(公告)号：US08543735B2
公开(公告)日：2013-09-24
申请号：US13618369
申请日：2012-09-14
申请人： Masaaki Hirano , Kunihiko Nishiyama
发明人： Masaaki Hirano , Kunihiko Nishiyama
IPC分类号： G06F3/00 , G06F13/36
CPC分类号： G06F13/385 , G06F12/02
摘要： There is provided a semiconductor device having a reduced number of external terminals allocated for address input to receive access from outside, while realizing a high-speed response to an access from outside. The semiconductor device employs, in order to allow other external devices to directly access resources it possesses in its own address space, in an external interface circuit, external terminals which input a part of the address signal required for access from outside, a supplementary register which supplements the upper portion of address information that has been input from the external terminals, a mode register accessible from outside, and an address control circuit which generates an address signal to access the address space in a form based on information input from the external terminals, required supplementary information, and mode information of the mode register.
摘要翻译：提供了一种半导体器件，其具有减少的用于地址输入的外部端子数量以从外部接收访问的外部端子，同时实现对来自外部的访问的高速响应。半导体器件为了允许其他外部设备在其自己的地址空间中直接访问其外部接口电路中的资源，输入外部接入所需的部分地址信号的外部端子，附加寄存器补充从外部端子输入的地址信息的上部，可从外部访问的模式寄存器，以及地址控制电路，其基于从外部端子输入的信息，生成以形式访问地址空间的地址信号，所需的补充信息和模式寄存器的模式信息。

8. 发明申请

US20110208878A1 SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM 失效
标题翻译：半导体器件和数据处理系统
公开(公告)号：US20110208878A1
公开(公告)日：2011-08-25
申请号：US13033641
申请日：2011-02-24
申请人： Masaaki HIRANO , Kunihiko Nishiyama
发明人： Masaaki HIRANO , Kunihiko Nishiyama
IPC分类号： G06F3/00
CPC分类号： G06F13/385 , G06F12/02
摘要： There is provided a semiconductor device having a reduced number of external terminals allocated for address input to receive access from outside, while realizing a high-speed response to an access from outside.The semiconductor device employs, in order to allow other external devices to directly access resources it possesses in its own address space, in an external interface circuit, external terminals which input a part of the address signal required for access from outside, a supplementary register which supplements the upper portion of address information that has been input from the external terminals, a mode register accessible from outside, and an address control circuit which generates an address signal to access the address space in a form based on information input from the external terminals, required supplementary information, and mode information of the mode register.
摘要翻译：提供了一种半导体器件，其具有减少的用于地址输入的外部端子数量以从外部接收访问的外部端子，同时实现对来自外部的访问的高速响应。半导体器件为了允许其他外部设备在其自己的地址空间中直接访问其外部接口电路中的资源，输入外部接入所需的部分地址信号的外部端子，附加寄存器补充从外部端子输入的地址信息的上部，可从外部访问的模式寄存器，以及地址控制电路，其基于从外部端子输入的信息，生成形式地访问地址空间的地址信号，所需的补充信息和模式寄存器的模式信息。

9. 发明申请

US20110072184A1 DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM 有权
标题翻译：数据处理设备和数据处理系统
公开(公告)号：US20110072184A1
公开(公告)日：2011-03-24
申请号：US12854284
申请日：2010-08-11
申请人： Shohei TATEYAMA , Takao YAMAUCHI , Eisaku TOMIDA , Kunihiko NISHIYAMA , Yasuyuki SUZUKI
发明人： Shohei TATEYAMA , Takao YAMAUCHI , Eisaku TOMIDA , Kunihiko NISHIYAMA , Yasuyuki SUZUKI
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/385
摘要： To provide a data processing device in which a plurality of CPUs can individually and independently communicate with different functions of a USB device using a single communication path. The data processing device is configured so that a USB host module to be coupled to a plurality of central processing units has a plurality of pipes to communicate with an arbitrary end point of a USB device coupled from the outside of the data processing device, the data processing device also includes an access control register to specify which central processing unit should have a right to control the pipe and specify to which extent a range of the content of setting of a function for the pipe should be allowed, and a USB host interface is controlled in accordance with the content of setting of the access control register.
摘要翻译：为了提供一种数据处理装置，其中多个CPU可以使用单个通信路径独立且独立地与USB设备的不同功能通信。数据处理装置被配置为使得要耦合到多个中央处理单元的USB主机模块具有多个管道以与从数据处理设备的外部耦合的USB设备的任意端点进行通信，数据处理装置还包括访问控制寄存器，以指定哪个中央处理单元应当具有控制管道的权利，并且指定应该允许管道功能的设置内容的范围在哪个范围内，并且USB主机接口是根据访问控制寄存器的设置内容进行控制。

10. 发明授权

US06434691B1 Cell phones with instruction pre-fetch buffers allocated to low bit address ranges and having validating flags 有权
公开(公告)号：US06434691B1
公开(公告)日：2002-08-13
申请号：US09824186
申请日：2001-04-03
申请人： Yasuyuki Murakami , Shigezumi Matsui , Kunihiko Nishiyama , Atsushi Kiuchi , Yuichi Takitsune
发明人： Yasuyuki Murakami , Shigezumi Matsui , Kunihiko Nishiyama , Atsushi Kiuchi , Yuichi Takitsune
IPC分类号： G06F938
摘要： In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of instruction buffers, flags each specific to each of instruction buffers, and a buffer controller circuit. The buffer controller circuit may allocate one of specific values that plural lower bits of an instruction address may take to each of the instruction buffers, and prefetch instructions to the instruction buffers each corresponding to a respective addresses designated to by the plural lower bits, from the address following a predetermined fetch address. The constitution for instruction prefetch as above may be implemented in a simpler manner than the controlling structure using address tags of a cache memory or the controlling structure using read-write pointer based on the counter in FIFO buffers.

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