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1. 发明申请

US20150058706A1 TIMING OPTIMIZATION FOR MEMORY DEVICES EMPLOYING ERROR DETECTION CODED TRANSACTIONS 有权
标题翻译：对使用错误检测代码交易的内存设备的时序优化
公开(公告)号：US20150058706A1
公开(公告)日：2015-02-26
申请号：US13997908
申请日：2012-03-26
申请人： Kuljit Singh Bains
发明人： Kuljit Singh Bains
IPC分类号： G06F11/10 , G06F3/06
CPC分类号： G06F11/1004 , G06F3/061 , G06F3/0653 , G06F3/0673 , G11C7/1006 , G11C7/222 , G11C11/4076 , G11C11/4096 , G11C29/023 , G11C29/028 , G11C29/42
摘要： Systems, methods, and apparatuses are directed to optimizing turnaround timing of successive transactions between a host and a memory device. The host includes framing logic that generates a write frame that includes a plurality of data bits and an error bit checksum that is appended at the end of the data bits. The host further includes a bus infrastructure configured to accommodate the transfer of the write frame to the memory device and logic that defines the turnaround time to begin at a time instant that immediately follows the transfer of the data bits of the write frame. The turnaround time measures the time delay at which a succeeding write frame is to be transferred. In this manner, the turnaround time is optimized to enable the earlier initiation of successive data operations, thereby reducing the overall latency of successive back-to-back transactions.
摘要翻译：系统，方法和装置旨在优化主机和存储设备之间的连续事务的周转时间。主机包括生成包括多个数据位的写入帧和在数据位结尾附加的错误位校验和的成帧逻辑。主机还包括总线基础设施，该总线基础设施被配置为适应写入帧到存储器设备的传送以及定义在紧接着写入帧的数据位的传送之后的时刻开始的周转时间的逻辑。周转时间测量后续写入帧要传输的时间延迟。以这种方式，优化周转时间以使得能够较早地启动连续的数据操作，从而减少连续的背靠背事务的整体等待时间。

2. 发明申请

US20130341790A1 INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT 有权
标题翻译：可互换的连接阵列，用于双面插槽
公开(公告)号：US20130341790A1
公开(公告)日：2013-12-26
申请号：US13888627
申请日：2013-05-07
申请人： Michael W. Leddige , Kuljit Singh Bains , John Thomas Sprietsma
发明人： Michael W. Leddige , Kuljit Singh Bains , John Thomas Sprietsma
IPC分类号： H01L23/498
CPC分类号： H01L23/49816 , G11C5/02 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H05K1/181 , H05K2201/10159 , H05K2201/10734 , H05K2203/1572 , Y02P70/611
摘要： A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed.
摘要翻译：存储器模块具有连接阵列。连接阵列以行和列排列，使得存在第一和第二外部列。可以互换第一和第二外柱中的连接，以优化在基板上的双面模块放置。还公开并要求保护其他实施例。

3. 发明授权

US09710323B2 Delay-compensated error indication signal 有权
公开(公告)号：US09710323B2
公开(公告)日：2017-07-18
申请号：US13997850
申请日：2012-03-31
申请人： Kuljit Singh Bains , George Vergis
发明人： Kuljit Singh Bains , George Vergis
IPC分类号： G06F11/00 , G06F11/10 , G11C29/42 , G11C5/04 , G11C7/10 , G11C29/44 , G11C29/04
CPC分类号： G06F11/10 , G06F11/108 , G11C5/04 , G11C7/1063 , G11C29/42 , G11C29/44 , G11C2029/0409 , G11C2029/0411
摘要： A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

4. 发明申请

US20140013168A1 DELAY-COMPENSATED ERROR INDICATION SIGNAL 有权
标题翻译：延迟补偿错误指示信号
公开(公告)号：US20140013168A1
公开(公告)日：2014-01-09
申请号：US13997850
申请日：2012-03-31
申请人： Kuljit Singh Bains , George Vergis
发明人： Kuljit Singh Bains , George Vergis
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , G06F11/108 , G11C5/04 , G11C7/1063 , G11C29/42 , G11C29/44 , G11C2029/0409 , G11C2029/0411
摘要： A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.
摘要翻译：存储器子系统具有耦合到命令/地址线和错误警报线的多个存储器件，误差警报线被延迟补偿以提供确定性警报信号定时。命令/地址线和错误警报线连接在存储器件和管理存储器件的存储器控制器之间。命令/地址线由存储器控制器驱动，错误警报线由存储器件驱动。

5. 发明授权

US09619316B2 Timing optimization for memory devices employing error detection coded transactions 有权
公开(公告)号：US09619316B2
公开(公告)日：2017-04-11
申请号：US13997908
申请日：2012-03-26
申请人： Kuljit Singh Bains
发明人： Kuljit Singh Bains
IPC分类号： G06F11/10 , G11C11/4096 , G11C29/42 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C29/02 , G06F3/06
CPC分类号： G06F11/1004 , G06F3/061 , G06F3/0653 , G06F3/0673 , G11C7/1006 , G11C7/222 , G11C11/4076 , G11C11/4096 , G11C29/023 , G11C29/028 , G11C29/42
摘要： Systems, methods, and apparatuses are directed to optimizing turnaround timing of successive transactions between a host and a memory device. The host includes framing logic that generates a write frame that includes a plurality of data bits and an error bit checksum that is appended at the end of the data bits. The host further includes a bus infrastructure configured to accommodate the transfer of the write frame to the memory device and logic that defines the turnaround time to begin at a time instant that immediately follows the transfer of the data bits of the write frame. The turnaround time measures the time delay at which a succeeding write frame is to be transferred. In this manner, the turnaround time is optimized to enable the earlier initiation of successive data operations, thereby reducing the overall latency of successive back-to-back transactions.

6. 发明授权

US08099687B2 Interchangeable connection arrays for double-sided DIMM placement 有权
标题翻译：可互换连接阵列，用于双面DIMM放置
公开(公告)号：US08099687B2
公开(公告)日：2012-01-17
申请号：US11899497
申请日：2007-09-05
申请人： Michael W. Leddige , Kuljit Singh Bains , John Thomas Sprietsma
发明人： Michael W. Leddige , Kuljit Singh Bains , John Thomas Sprietsma
IPC分类号： G06F17/50
CPC分类号： H01L23/49816 , G11C5/02 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H05K1/181 , H05K2201/10159 , H05K2201/10734 , H05K2203/1572 , Y02P70/611
摘要： A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate.
摘要翻译：存储器模块具有连接阵列。连接阵列以行和列排列，使得存在第一和第二外部列。可以互换第一和第二外柱中的连接，以优化在基板上的双面模块放置。

7. 发明申请

US20140301152A1 REDUCTION OF POWER CONSUMPTION IN MEMORY DEVICES DURING REFRESH MODES 有权
标题翻译：在刷新模式下减少存储器件中的功耗
公开(公告)号：US20140301152A1
公开(公告)日：2014-10-09
申请号：US13997959
申请日：2012-03-27
申请人： Christopher E. Cox , Kuljit Singh Bains , John B. Halbert
发明人： Christopher E. Cox , Kuljit Singh Bains , John B. Halbert
IPC分类号： G11C11/406
CPC分类号： G11C11/40615 , G11C7/00 , G11C7/08 , G11C11/40611 , G11C11/4074 , G11C11/409 , G11C11/4096 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C2211/4065 , G11C2211/4068
摘要： Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.
摘要翻译：设备，系统和方法包括适应存储器件的读/写操作和自刷新模式的主动模式，以适应当读/写操作空闲时表示存储数据的电压电平的再充电。至少一个寄存器源提供小于第一电压电平的第一电压电平和第二电压电平。通过这样的配置，在活动模式期间，存储器件以由至少一个寄存器源提供的第一电压电平工作，并且在自刷新模式期间，存储器件以由第二电压电平至少一个寄存器源。

8. 发明授权

US08438515B2 Interchangeable connection arrays for double-sided DIMM placement 有权
标题翻译：可互换连接阵列，用于双面DIMM放置
公开(公告)号：US08438515B2
公开(公告)日：2013-05-07
申请号：US13339525
申请日：2011-12-29
申请人： Michael W. Leddige , Kuljit Singh Bains , John Thomas Sprietsma
发明人： Michael W. Leddige , Kuljit Singh Bains , John Thomas Sprietsma
IPC分类号： G06F17/50
CPC分类号： H01L23/49816 , G11C5/02 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H05K1/181 , H05K2201/10159 , H05K2201/10734 , H05K2203/1572 , Y02P70/611
摘要： A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed.
摘要翻译：存储器模块具有连接阵列。连接阵列以行和列排列，使得存在第一和第二外部列。可以互换第一和第二外柱中的连接，以优化在基板上的双面模块放置。还公开并要求保护其他实施例。

9. 发明申请

US20120199973A1 INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT 有权
标题翻译：可互换的连接阵列，用于双面插槽
公开(公告)号：US20120199973A1
公开(公告)日：2012-08-09
申请号：US13339525
申请日：2011-12-29
申请人： Michael W. Leddige , Kuljit Singh Bains , John Thomas Sprietsma
发明人： Michael W. Leddige , Kuljit Singh Bains , John Thomas Sprietsma
IPC分类号： H01L23/498
CPC分类号： H01L23/49816 , G11C5/02 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H05K1/181 , H05K2201/10159 , H05K2201/10734 , H05K2203/1572 , Y02P70/611
摘要： A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed.
摘要翻译：存储器模块具有连接阵列。连接阵列以行和列排列，使得存在第一和第二外部列。可以互换第一和第二外柱中的连接，以优化在基板上的双面模块放置。还公开并要求保护其他实施例。

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