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1. 发明授权

US5323352A Refresh control circuit for memory 失效
标题翻译：刷新内存控制电路
公开(公告)号：US5323352A
公开(公告)日：1994-06-21
申请号：US754764
申请日：1991-09-04
申请人： Souichi Miyata , Kouichi Hatakekyama , Tsuyoshi Muramatsu
发明人： Souichi Miyata , Kouichi Hatakekyama , Tsuyoshi Muramatsu
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A refresh control circuit includes a refresh request generating circuit, a multiplexer, a memory access control circuit and an elimination control circuit. The refresh request generating circuit periodically outputs a transfer pulse and a refresh packet for refreshing. The merging control circuit receives a transfer pulse for normal access and a transfer pulse for refreshing. The merging control circuit, when the transfer pulse for refreshing and the transfer pulse for normal access contend with each other, applies first the transfer pulse to the memory access control circuit, makes the other stand by and generates an identification signal for identifying normal access and refreshing. The multiplexer receives a refresh packet and a data packet and applies one of the packets to the memory access control circuit in response to the identification signal. The memory access control circuit selectively controls a normal access operation based on the data packet or a refresh operation based on the refresh packet in response to the identification signal to output a transfer pulse. When an identification signal indicates a refresh operation, the elimination control circuit eliminates a transfer pulse output from the memory access control circuit.
摘要翻译：刷新控制电路包括刷新请求生成电路，复用器，存储器访问控制电路和消除控制电路。刷新请求生成电路周期性地输出用于刷新的传送脉冲和刷新包。合并控制电路接收用于正常访问的传送脉冲和用于刷新的传送脉冲。合并控制电路，当用于刷新的传送脉冲和用于正常访问的传送脉冲相互抵触时，首先将传送脉冲施加到存储器访问控制电路，使另一个备用并产生用于识别正常访问的识别信号，清爽复用器接收刷新分组和数据分组，并响应于识别信号将一个分组应用于存储器访问控制电路。存储器访问控制电路响应于识别信号，选择性地基于数据包或基于刷新包的刷新操作来控制正常访问操作，以输出传送脉冲。当识别信号指示刷新操作时，消除控制电路消除从存储器访问控制电路输出的传送脉冲。

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