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1. 发明申请

US20080022040A1 Cache memory system 有权
标题翻译：缓存存储系统
公开(公告)号：US20080022040A1
公开(公告)日：2008-01-24
申请号：US11826496
申请日：2007-07-16
申请人： Seimizu Joukan , Tomohiro Hirata , Kiyoshi Owada
发明人： Seimizu Joukan , Tomohiro Hirata , Kiyoshi Owada
IPC分类号： G06F12/00
CPC分类号： G06F12/1054 , G06F12/0864
摘要： The cache memory system 1 comprises: a virtual index obtaining unit 13 operable to obtain, based on a virtual address, virtual indexes of an access-target cache line and a cache line potentially having a cache-aliasing relationship with the access-target cache line; a physical tag obtaining unit 15 operable to obtain a physical tag of a physical page by performing address translation on the virtual address; and a comparing unit 16 operable to compare a physical tag TAG obtained by the physical tag obtaining unit 15 with each tag information piece TAG(i) belonging to cache lines corresponding to the virtual indexes and output from the tag array 11a based on the virtual indexes obtained by the virtual index obtaining unit 13, and determines a cache hit/miss.
摘要翻译：高速缓冲存储器系统1包括：虚拟索引获取单元13，可操作以基于虚拟地址获得可能与访问目标高速缓存行具有高速缓存混叠关系的访问目标高速缓存行和高速缓存行的虚拟索引 ; 物理标签获取单元15，用于通过在虚拟地址上执行地址转换来获得物理页面的物理标签; 以及比较单元16，其可操作以将由物理标签获取单元15获得的物理标签TAG与属于与虚拟索引对应的高速缓存线的每个标签信息片段TAG（i）进行比较，并且基于虚拟索引从标签阵列11a输出由虚拟索引获取单元13获得的索引，并确定高速缓存命中/未命中。

2. 发明授权

US06457174B1 Program linking apparatus for linking and executing one program and another program using a microprocessor and a program linking method thereof 失效
标题翻译：用于链接并执行一个程序的程序链接装置和使用微处理器的程序链接方法和程序链接方法
公开(公告)号：US06457174B1
公开(公告)日：2002-09-24
申请号：US09426570
申请日：1999-10-22
申请人： Toyoharu Kuroda , Kiyoshi Owada , Yoshihiko Motohashi
发明人： Toyoharu Kuroda , Kiyoshi Owada , Yoshihiko Motohashi
IPC分类号： G06F944
CPC分类号： G06F8/54
摘要： A code export symbol offset table A 1128 stores sets of the identifier and the offset of the area of a code symbol. In an export symbol import step 1160, the identifier that matches the identifier of a symbol is retrieved from the code export symbol offset table A 1128, the offset corresponding to the retrieved identifier is extracted, and a predetermined calculation is performed to create an absolute address.
摘要翻译：代码输出符号偏移表A 1128存储标识符的集合和代码符号的区域的偏移。在导出符号导入步骤1160中，从代码导出符号偏移表A 1128检索与符号的标识符匹配的标识符，提取与检索到的标识符相对应的偏移量，并执行预定的计算以创建绝对地址。

3. 发明授权

US6125428A Apparatus for reproducing multimedia data, method for reproducing multimedia data, and record media containing multimedia data reproduction program 失效
标题翻译：用于再现多媒体数据的装置，用于再现多媒体数据的方法，以及记录包含多媒体数据再现程序的媒体
公开(公告)号：US6125428A
公开(公告)日：2000-09-26
申请号：US28486
申请日：1998-02-24
申请人： Masaya Miyazaki , Kiyoshi Owada , Nobuyuki Enoki
发明人： Masaya Miyazaki , Kiyoshi Owada , Nobuyuki Enoki
IPC分类号： G06F17/30 , G11B27/00 , G11B27/36 , G06F12/00
CPC分类号： G06F17/30017 , G11B27/002 , G11B27/36 , G11B2220/20 , G11B2220/41 , Y10S707/99953 , Y10S707/99956
摘要： A multimedia data reproduction apparatus comprising an optical disk library containing a plurality of optical disks and a plurality of optical disk drives, a file management unit for managing names of motion picture files stored in the respective optical disks, a media management unit for managing whether each of the optical disks is being used or not, a drive management unit for managing whether each of the optical disk drives is being used or not, an open processing unit for deciding whether to accept a request to start reading or reject it according to information from the file management unit, media management unit and the drive management unit, a close processing unit for performing close processing of a motion picture file for which a request to end reading is issued, a data readout control unit for reading motion picture data in response to the request to start reading, and a network control unit for controlling communication between the above-mentioned units and terminal PCs 20. In this apparatus, it is possible to continuously reproduce motion pictures from the optical disk library.
摘要翻译：一种多媒体数据再现装置，包括包含多个光盘的光盘库和多个光盘驱动器，用于管理存储在各个光盘中的运动图像文件的名称的文件管理单元，用于管理每个正在使用光盘的驱动器管理单元，用于管理是否正在使用光盘驱动器的驱动管理单元，用于根据来自...的信息决定是否接受开始读取或拒绝的请求的开放处理单元文件管理单元，媒体管理单元和驱动器管理单元，用于对发出结束读取请求的运动图像文件执行关闭处理的关闭处理单元，响应于开始读取的请求以及用于控制上述单元与终端PC 20之间的通信的网络控制单元在该装置中，可以从光盘库连续地再现运动图像。

4. 发明授权

US07441240B2 Process scheduling apparatus, process scheduling method, program for process scheduling, and storage medium recording a program for process scheduling 失效
标题翻译：处理调度装置，处理调度方法，进程调度程序以及记录程序进程调度的存储介质
公开(公告)号：US07441240B2
公开(公告)日：2008-10-21
申请号：US10750852
申请日：2004-01-05
申请人： Katsushige Amano , Tetsuji Yamamoto , Kiyoshi Owada , Hiroyuki Machida , Takao Shinohara
发明人： Katsushige Amano , Tetsuji Yamamoto , Kiyoshi Owada , Hiroyuki Machida , Takao Shinohara
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/4812
摘要： A process scheduling apparatus has a delayed task handling process for processing delayed tasks having variable priorities and multiple other processes for handling processes other than delayed tasks. Fixed priorities are assigned to the other processes. The process scheduler sequentially executes the delayed task handling process and the other processes according the assigned priorities. A delayed task registration processor stores newly generated delayed tasks with assigned priorities in a queuing table. A delayed task priority controller selects the delayed task with the highest priority in the queuing table. A process priority controller sets the priority of the delayed task handling process to the same priority as the priority of the delayed task with the highest priority.
摘要翻译：处理调度装置具有用于处理具有可变优先级的延迟任务的延迟任务处理过程和用于处理除延迟任务之外的处理的多个其他进程。固定的优先级分配给其他进程。进程调度器根据分配的优先级顺序地执行延迟的任务处理过程和其他进程。延迟任务注册处理器将具有分配优先级的新生成的延迟任务存储在排队表中。延迟任务优先级控制器在排队表中选择具有最高优先级的延迟任务。进程优先级控制器将延迟任务处理进程的优先级设置为与优先级最高的延迟任务的优先级相同的优先级。

5. 发明授权

US07171549B2 Information processing apparatus for start-up of an operating system using three different initialization modes in a specific sequence 有权
标题翻译：用于以特定顺序使用三种不同的初始化模式启动操作系统的信息处理装置
公开(公告)号：US07171549B2
公开(公告)日：2007-01-30
申请号：US10745513
申请日：2003-12-29
申请人： Hiroyuki Machida , Takao Shinohara , Kiyoshi Owada , Tetsuji Yamamoto , Katsushige Amano
发明人： Hiroyuki Machida , Takao Shinohara , Kiyoshi Owada , Tetsuji Yamamoto , Katsushige Amano
IPC分类号： G06F15/177
CPC分类号： G06F9/4406
摘要： To start up an operating system (OS), CPU performs initializations in three modes: The three modes include a first I/O initialization (Early init) (132) which is to be done serially when no threads are yet usable, without any advanced technique and with a long wait time until a next operation can be made; a second I/O initialization (136) which is to be done when threads are usable, in a plurality of steps parallelized with each other using the usable threads according to the dependency relation between devices to be initialized and with synchronization between the steps each by a barrier; and a third I/O initialization (Lazy init) (140) in which remaining initializations are done in parallel with each other using the threads commensurately to a user process when the user process becomes executable. The present invention is applicable to home-use electric or electronic appliances.
摘要翻译：要启动操作系统（OS），CPU以三种模式执行初始化：三种模式包括第一个I / O初始化（Early init）（132），当没有线程可用时，它将被串行完成，没有任何高级技术和等待时间长，直到下一个操作可以进行; 根据要初始化的设备之间的依赖关系，并且各步骤之间的同步，使用可使用的线程在多个并行化的步骤中进行线程可用的第二I / O初始化（136）一个障碍以及第三个I / O初始化（Lazy init）（140），其中当用户进程变得可执行时，使用与用户进程相当的线程彼此并行地完成剩余的初始化。本发明适用于家用电器或电子设备。

6. 发明申请

US20050074022A1 Data transmitting apparatus and data receiving apparatus 审中-公开
标题翻译：数据发送装置和数据接收装置
公开(公告)号：US20050074022A1
公开(公告)日：2005-04-07
申请号：US10415387
申请日：2001-11-01
申请人： Naoe Kato , Yusuke Mizuno , Keishi Sugimoto , Kohji Okuno , Kiyoshi Owada
发明人： Naoe Kato , Yusuke Mizuno , Keishi Sugimoto , Kohji Okuno , Kiyoshi Owada
IPC分类号： G06Q10/00 , G06F9/445 , G06Q30/00 , H04N7/08 , H04N7/081 , H04N7/16 , H04N21/2343 , H04N21/2347 , H04N21/235 , H04N21/2543 , H04N21/258 , H04N21/435 , H04N21/45 , H04N21/454 , H04N21/81 , H04J3/26
CPC分类号： H04N21/4351 , H04N7/165 , H04N21/23439 , H04N21/23476 , H04N21/2358 , H04N21/2543 , H04N21/25833 , H04N21/4516 , H04N21/454 , H04N21/8166
摘要： A data transmitting apparatus for transmitting data to a plurality of data receiving apparatuses comprises acquiring means, organizing means, and transmitting means. The acquiring means acquires a plurality of sets of selection data, each set of which is targeted for one data receiving apparatus model. The organizing means compares the plurality of sets of selection data and extracts common data and unique data. The common data is a portion of one set of selection data that is also contained in one or more other sets of selection data, and the unique data is a remaining portion in each set of selection data left after excluding the common data. The transmitting means transmits the common data and the unique data together to the plurality of data receiving apparatuses.
摘要翻译：一种数据发送装置，用于向多个数据接收装置发送数据，包括获取装置，组织装置和发送装置。获取装置获取多组选择数据，每组选择数据是针对一个数据接收装置模型的。组织装置比较多组选择数据并提取公共数据和唯一数据。公共数据是也包含在一个或多个其他选择数据集合中的一组选择数据的一部分，唯一数据是排除公共数据之后剩下的每组选择数据中的剩余部分。发送装置将公共数据和唯一数据一起发送到多个数据接收装置。

7. 发明授权

US07870325B2 Cache memory system 有权
标题翻译：缓存存储系统
公开(公告)号：US07870325B2
公开(公告)日：2011-01-11
申请号：US11826496
申请日：2007-07-16
申请人： Seimizu Joukan , Tomohiro Hirata , Kiyoshi Owada
发明人： Seimizu Joukan , Tomohiro Hirata , Kiyoshi Owada
IPC分类号： G06F12/00
CPC分类号： G06F12/1054 , G06F12/0864
摘要： The cache memory system 1 comprises: a virtual index obtaining unit 13 operable to obtain, based on a virtual address, virtual indexes of an access-target cache line and a cache line potentially having a cache-aliasing relationship with the access-target cache line; a physical tag obtaining unit 15 operable to obtain a physical tag of a physical page by performing address translation on the virtual address; and a comparing unit 16 operable to compare a physical tag TAG obtained by the physical tag obtaining unit 15 with each tag information piece TAG(i) belonging to cache lines corresponding to the virtual indexes and output from the tag array 11a based on the virtual indexes obtained by the virtual index obtaining unit 13, and determines a cache hit/miss.
摘要翻译：高速缓冲存储器系统1包括：虚拟索引获取单元13，可操作以基于虚拟地址获得可能与访问目标高速缓存行具有高速缓存混叠关系的访问目标高速缓存行和高速缓存行的虚拟索引 ; 物理标签获取单元15，用于通过在虚拟地址上执行地址转换来获得物理页面的物理标签; 以及比较单元16，其可操作以将由物理标签获取单元15获得的物理标签TAG与属于与虚拟索引对应的高速缓存行的标签信息块TAG（i）和基于虚拟索引从标签阵列11a输出由虚拟索引获取单元13获得，并确定高速缓存命中/未命中。

8. 发明授权

US07363622B2 Remote program downloading system 有权
标题翻译：远程程序下载系统
公开(公告)号：US07363622B2
公开(公告)日：2008-04-22
申请号：US10105302
申请日：2002-03-26
申请人： Kiyoshi Owada
发明人： Kiyoshi Owada
IPC分类号： G06F9/44
CPC分类号： G06F8/658
摘要： In this system, program data is generated by configuring a plurality of modules based on a relationship between dependence of the modules composing the program. Then, generated two versions of program data is compared starting from a head address of each of the program data, and data at an address, and thereafter, where the data first makes a difference is extracted to generate difference data. Further, a center holds the latest version of program and at least one item of difference data, and transmits the whole data of program or difference data corresponding to a program version in a terminal apparatus, and the program is updated in the terminal apparatus using the received data.
摘要翻译：在该系统中，通过基于构成程序的模块的依赖关系来配置多个模块来生成程序数据。然后，从节目数据中的每一个的头地址和地址的数据开始生成两个版本的节目数据，然后提取数据首先产生差异的数据，以生成差分数据。此外，中心保存最新版本的程序和至少一个差分数据项目，并且在终端装置中发送对应于节目版本的节目或差异数据的整个数据，并且在终端装置中使用收到的资料。

9. 发明授权

US07107407B2 Arithmetic unit with reduced startup time and method of loading data 有权
标题翻译：减少启动时间的算术单元和加载数据的方法
公开(公告)号：US07107407B2
公开(公告)日：2006-09-12
申请号：US10680128
申请日：2003-10-08
申请人： Shinsuke Kato , Kiyoshi Owada
发明人： Shinsuke Kato , Kiyoshi Owada
IPC分类号： G06F12/08
CPC分类号： G06F9/4403
摘要： An arithmetic unit includes a switching device 16 and a cache controller 19. The switching device 16 determines whether desired data to be read by the CPU 11 is in a RAM 14, and allows, depending on a result of the determination, the CPU 11 to directly read the desired data from a ROM 13. The cache controller 19 controls a cache 12 so that the RAM 14 is initialized based on cache data corresponding to the desired data stored in the cache 12. In an arithmetic unit having a CPU, a cache, RAM, and ROM configured in the above manner, the time required for a startup process is reduced.
摘要翻译：算术单元包括切换装置16和高速缓存控制器19.切换装置16确定要由CPU 11读取的期望数据是否在RAM14中，并且根据确定结果允许CPU 11至从ROM13直接读取所需的数据。高速缓存控制器19控制高速缓存12，使得RAM14基于与存储在高速缓存12中的所需数据相对应的高速缓存数据来初始化。在具有CPU的运算单元中，高速缓存，RAM和ROM，则启动处理所需的时间减少。

10. 发明授权

US06611902B2 Information processor and information processing method 失效
公开(公告)号：US06611902B2
公开(公告)日：2003-08-26
申请号：US09964604
申请日：2001-09-28
申请人： Toyoharu Kuroda , Kiyoshi Owada
发明人： Toyoharu Kuroda , Kiyoshi Owada
IPC分类号： G06F1200
CPC分类号： G06F11/1433 , G06F8/4434 , G06F9/445 , G06F11/1469
摘要： The present invention provides an information processor and an information processing method, which reduces the memory capacity and utilizes a free space in a memory area as a cache area for EPG. This information processor includes a program obtaining means 5, a program storage means 2 which has plural storage areas, a program execution means 13, a selection information updating means 11 that stores execution memory information indicating a storage area which contains a program to be executed by the program execution means 13, compression information which indicates compression states of programs stored in the storage areas, and memory relation information which indicates the relation of the plural storage areas, a program execution area switching means 4 for selecting one of the storage areas on the basis of the execution memory information, a storage area switching means 3 for selecting one of the storage areas on the basis of the information in the selection information updating means 11, a program writing means 6, a program compression means 7, a program restoration means 12 for restoring a program which has been compressed by the program compression means 7, and a memory information updating means 8 for updating information stored in the selection information updating means 11.

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