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1. 发明授权

US06403461B1 Method to reduce capacitance between metal lines 有权
标题翻译：降低金属线之间电容的方法
公开(公告)号：US06403461B1
公开(公告)日：2002-06-11
申请号：US09912606
申请日：2001-07-25
申请人： Kim-Hyun Tae , Chok-Kho Liep , Choi-Byoung Il
发明人： Kim-Hyun Tae , Chok-Kho Liep , Choi-Byoung Il
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L21/7682 , H01L21/76885 , H01L23/5222 , H01L23/5329 , H01L2221/1026 , H01L2924/0002 , H01L2924/00
摘要： A process for reducing device capacitance via inclusion of an air gap in a low dielectric constant (low k), layer, used to fill narrow spaces between metal lines, has been developed. The process features the formation of dual damascene metal lines, comprised with a narrow space between the top portions of the dual damascene metal structures, and a wider space between bottom portions of these same structures. Deposition of a low k layer, using a deposition procedure lacking acceptable conformality properties, results in the narrow space between top portions of the dual damascene metal structures being completely filled with low k layer, while the wider space located between bottom portions of the metal structures remains unfilled. The unfilled portion of the low k layer now features an embedded air gap, resulting in decreased capacitance for the dielectric layer located between metal lines, thus reducing performance degrading RC delays.
摘要翻译：已经开发了用于通过包含用于填充金属线之间的狭窄空间的低介电常数（低k）层中的气隙来降低器件电容的工艺。该方法的特征在于形成双镶嵌金属线，其包括在双镶嵌金属结构的顶部之间的狭窄空间以及这些相同结构的底部之间较宽的空间。使用不具有可接受的共形特性的沉积程序沉积低k层导致双镶嵌金属结构的顶部之间的狭窄空间被完全填充低k层，而位于金属结构的底部之间的较宽空间仍未填写低k层的未填充部分现在具有嵌入的气隙，导致位于金属线之间的电介质层的电容降低，从而降低了RC延迟的性能。

2. 发明授权

US06350695B1 Pillar process for copper interconnect scheme 失效
标题翻译：铜互连方案的支柱工艺
公开(公告)号：US06350695B1
公开(公告)日：2002-02-26
申请号：US09594414
申请日：2000-06-16
申请人： Kim Hyun Tae , Kim Hock Ang , Kiok Boone Elgin Quek
发明人： Kim Hyun Tae , Kim Hock Ang , Kiok Boone Elgin Quek
IPC分类号： H01L21311
CPC分类号： H01L21/76885
摘要： A method for forming reliable inter-level metal interconnections in semiconductor integrated circuits is described where pillars are formed to connect between different metal layers. A first conductive layer is deposited overlying a substrate. A conductive etch stop layer is deposited overlying the first conductive layer and then patterned to form a mask for the fist conductive layer. This is followed by a deposition of via metal layer overlying the entire surface. A hard mask layer is deposited and patterned to form the mask where via pillars are to be formed. Subsequent anisotropic etching forms pillars in the via met layer and openings in the first conductive layer. An inter-metal dielectric (IMD) layer is deposited covering and filling both the openings in the first conductive layer and in between the via pillars. The surface is then planarized.
摘要翻译：描述了在半导体集成电路中形成可靠的层间金属互连的方法，其中形成支柱以在不同的金属层之间连接。沉积在衬底上的第一导电层。沉积覆盖在第一导电层上的导电蚀刻停止层，然后将其图案化以形成用于第一导电层的掩模。之后是覆盖整个表面的通孔金属层的沉积。沉积硬掩模层并图案化以形成要形成通孔柱的掩模。随后的各向异性蚀刻在通孔结合层中形成柱状并在第一导电层中形成开口。沉积金属间电介质（IMD）层，其覆盖并填充第一导电层中的开口和通孔之间的两个开口。然后将表面平坦化。

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