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1. 发明申请

US20080218782A1 IMAGE PROCESSING APPARATUS 有权
标题翻译：图像处理设备
公开(公告)号：US20080218782A1
公开(公告)日：2008-09-11
申请号：US12042091
申请日：2008-03-04
申请人： Takeshi SEKI , Tomohiro Fukuoka , Kiichiro Iga , Yuji Watarai
发明人： Takeshi SEKI , Tomohiro Fukuoka , Kiichiro Iga , Yuji Watarai
IPC分类号： G06F15/00
CPC分类号： G06T5/002 , G06T5/003 , G06T5/20 , G06T7/13 , G06T2207/10024 , G06T2207/20012 , G06T2207/20032 , G06T2207/20192
摘要： An image processing system is disclosed that includes a buffer unit configured to store a predetermined pixel and peripheral pixels neighboring the predetermined pixel in image data in a first direction and a second direction perpendicular to the first direction; and a first edge-detecting circuit configured to calculate a maximum value and a minimum value of a set of pixels selected from the peripheral pixels that have the same color as the predetermined pixel to calculate a difference value between the maximum value and the minimum value.
摘要翻译：公开了一种图像处理系统，其包括：缓冲单元，被配置为在垂直于第一方向的第一方向和第二方向上存储与图像数据中的预定像素相邻的预定像素和外围像素; 以及第一边缘检测电路，被配置为计算从与所述预定像素具有相同颜色的周边像素中选择的一组像素的最大值和最小值，以计算最大值和最小值之间的差值。

2. 发明申请

US20070268503A1 Image processing system 审中-公开
标题翻译：图像处理系统
公开(公告)号：US20070268503A1
公开(公告)日：2007-11-22
申请号：US11797554
申请日：2007-05-04
申请人： Takeshi Seki , Tomohiro Fukuoka , Kiichiro Iga , Yuji Watarai
发明人： Takeshi Seki , Tomohiro Fukuoka , Kiichiro Iga , Yuji Watarai
IPC分类号： G06F15/00
CPC分类号： G06T5/002 , G06T5/20 , G06T2207/20192 , H04N5/357
摘要： An image processing system 1 comprises: a buffer 2 for storing a target pixel oo that is an object of image processing and a group of pixels surrounding the target pixel oo, such that the pixels are aligned in horizontal and vertical directions; a maximum value detector 31 for obtaining a maximum value Bmax from pixels of the surrounding pixel group which pixels have the same color as the target pixel oo; a minimum value detector 32 for obtaining a minimum value Bmin from the pixels of the surrounding pixel group which pixels have the same color as the target pixel oo; and a subtracter 33 for subtracting a result obtained by the minimum value detector 32 from a result obtained by the maximum value detector 31.
摘要翻译：图像处理系统1包括：缓冲器2，用于存储作为图像处理对象的目标像素oo和围绕目标像素oo的像素组，使得像素在水平和垂直方向上对准; 最大值检测器31，用于从像素与目标像素oo具有相同颜色的周围像素组的像素获得最大值Bmax; 最小值检测器32，用于从像素与目标像素oo具有相同颜色的周围像素组的像素获得最小值Bmin; 以及用于从由最大值检测器31获得的结果中减去由最小值检测器32获得的结果的减法器33。

3. 发明申请

US20070132883A1 On-screen display device and control method therefor 审中-公开
标题翻译：屏幕显示装置及其控制方法
公开(公告)号：US20070132883A1
公开(公告)日：2007-06-14
申请号：US11398689
申请日：2006-04-06
申请人： Nobuyuki Hattori , Kazuhiko Okada , Chihiro Sekiya , Kiichiro Iga
发明人： Nobuyuki Hattori , Kazuhiko Okada , Chihiro Sekiya , Kiichiro Iga
IPC分类号： H04N11/00
CPC分类号： G09G5/397 , G09G2340/12
摘要： An OSD device is provided which allows a reduction in the capacity of a memory for storing OSD data and also allows the efficient use of a transfer frequency band in the transfer of the OSD data. A management information data set MD includes, for the display position of each of OSD data sets OD to be superimposed on sensed image data sets SD, display position information sets HDISP and VDISP on the OSD data set OD and a storage location information set WORD on the OSD data set OD. The on-screen display device comprises an OSD data storage region (32) for storing the OSD data sets OD, senses the management information data set MD having HDISP and VDISP which match the display position of each of the sensed image data sets SD, and retrieves the OSD data sets stored in WORD included in the management information data set MD from the OSD data storage region (32).
摘要翻译：提供一种OSD装置，其允许降低用于存储OSD数据的存储器的容量，并且还允许在OSD数据的传送中有效地使用传送频带。管理信息数据组MD包括：对于要叠加在感测图像数据集SD上的每个OSD数据集OD的显示位置，OSD数据集OD上的显示位置信息集HDISP和VDISP以及存储位置信息集WORD OSD数据集OD。屏幕显示装置包括用于存储OSD数据组OD的OSD数据存储区域（32），感测具有与每个感测图像数据集SD的显示位置相匹配的HDISP和VDISP的管理信息数据集MD，以及从OSD数据存储区域（32）检索存储在包含在管理信息数据组MD中的WORD中的OSD数据集。

4. 发明申请

US20060244992A1 Image processor of imaging apparatus 失效
标题翻译：成像设备的图像处理器
公开(公告)号：US20060244992A1
公开(公告)日：2006-11-02
申请号：US11241930
申请日：2005-10-04
申请人： Kiichiro Iga , Tomohiro Fukuoka
发明人： Kiichiro Iga , Tomohiro Fukuoka
IPC分类号： G06F3/12 , G06F15/00
CPC分类号： H04N19/625 , H04N19/60 , H04N19/91
摘要： A format conversion circuit converts RGB data to YCbCr data. A one-dimensional compression circuit performs one-dimensional compression process on the YCbCr data to generate one-dimension compression image data and provides the one-dimension compression image data to a base band LSI. The one-dimensional compression circuit includes a memory area that is relatively small but sufficient for holding several bytes of data subject to the compression process.
摘要翻译：格式转换电路将RGB数据转换为YCbCr数据。一维压缩电路对YCbCr数据执行一维压缩处理以产生一维压缩图像数据，并将一维压缩图像数据提供给基带LSI。一维压缩电路包括相对较小但足以容纳经受压缩处理的几个字节的数据的存储器区域。

5. 发明申请

US20060061601A1 Image processing circuit and image processing method 有权
标题翻译：图像处理电路和图像处理方法
公开(公告)号：US20060061601A1
公开(公告)日：2006-03-23
申请号：US11037265
申请日：2005-01-19
申请人： Kiichiro Iga , Chihiro Sekiya
发明人： Kiichiro Iga , Chihiro Sekiya
IPC分类号： H04N9/74 , G09G5/00
CPC分类号： G06T3/4023 , H04N5/0675
摘要： The invention provides an image processing circuit having a capability of performing a reduction (resizing) process and an enlargement process on horizontal-scanning-line data inputted in synchronization with an input horizontal synchronization signal, and subsequently adjusting the horizontal synchronization signals so that the input horizontal-scanning-line data is made transferable to external devices in real time, and an image processing method therefor. A reducing unit thins out n-lines of the input horizontal synchronization signals out of m-lines of the input horizontal synchronization signals HD. When an enlarging unit enlarges the image data by an enlargement ratio k (k: natural number) in the vertical direction, the enlarging unit inserts (k−1) lines of the second horizontal synchronization signals for data transmission EHSYNC2 in the transmitting horizontal-synchronization-signal interval time TC1 between adjacent first horizontal synchronization signals for data. transmission EHSYNC1 with predetermined intervals. A composing unit merges the first horizontal synchronization signals for data transmission EHSYNC1 and the second horizontal synchronization signals for data transmission EHSYNC2 to give horizontal synchronization signals for data transmission EHSYNC.
摘要翻译：本发明提供一种图像处理电路，其具有与输入的水平同步信号同步地输入的水平扫描线数据进行缩小（调整大小）处理和放大处理的能力，随后调整水平同步信号，使得输入水平扫描线数据可实时传送到外部设备，以及其图像处理方法。减少单元在输入的水平同步信号HD的m行中消除输入水平同步信号的n行。当放大单元通过垂直方向上的放大率k（k：自然数）放大图像数据时，放大单元将用于数据发送的第二水平同步信号EHSYNC 2的（k-1）行插入到发送水平方向相邻的第一个水平同步信号之间的数据同步信号间隔时间TC 1。传输EHSYNC 1以预定间隔。组合单元合并用于数据传输EHSYNC 1的第一水平同步信号和用于数据传输EHSYNC 2的第二水平同步信号，以给出用于数据传输EHSYNC的水平同步信号。

6. 发明申请

US20050174437A1 Distortion correction circuit 有权
标题翻译：失真校正电路
公开(公告)号：US20050174437A1
公开(公告)日：2005-08-11
申请号：US10937478
申请日：2004-09-10
申请人： Kiichiro Iga
发明人： Kiichiro Iga
IPC分类号： G06T3/00 , H04N5/228 , H04N5/232 , H04N101/00
CPC分类号： H04N5/3572
摘要： A circuit for correcting distortion produced by the lens of a digital camera when generating an image, which includes pixels. The correction circuit includes an address generation circuit for generating horizontal and vertical addresses for each pixel. A coefficient storage circuit stores a pitch correction coefficient associated with the horizontal or vertical address of each pixel. A storage circuit stores data for an image for which distortion is uncorrected in association with an address of the uncorrected image. A calculation circuit calculates the address of data of the uncorrected image corresponding to each pixel using the associated horizontal and vertical addresses and pitch correction coefficient of the horizontal or vertical address. A processing circuit reads the data of the uncorrected image from the storage circuit and generates data for a distortion-corrected image.
摘要翻译：一种用于在产生包括像素的图像时校正由数字照相机的透镜产生的失真的电路。校正电路包括用于为每个像素生成水平和垂直地址的地址产生电路。系数存储电路存储与每个像素的水平或垂直地址相关联的音调校正系数。存储电路与未校正图像的地址相关联地存储未校正失真的图像的数据。计算电路使用相关的水平和垂直地址以及水平或垂直地址的音调校正系数来计算对应于每个像素的未校正图像的数据的地址。处理电路从存储电路读取未校正图像的数据，并生成用于失真校正图像的数据。

7. 发明授权

US08194984B2 Image processing system that removes noise contained in image data 有权
标题翻译：去除图像数据中包含的噪点的图像处理系统
公开(公告)号：US08194984B2
公开(公告)日：2012-06-05
申请号：US12042091
申请日：2008-03-04
申请人： Takeshi Seki , Tomohiro Fukuoka , Kiichiro Iga , Yuji Watarai
发明人： Takeshi Seki , Tomohiro Fukuoka , Kiichiro Iga , Yuji Watarai
IPC分类号： G06K9/48
CPC分类号： G06T5/002 , G06T5/003 , G06T5/20 , G06T7/13 , G06T2207/10024 , G06T2207/20012 , G06T2207/20032 , G06T2207/20192
摘要： An image processing system is disclosed that includes a buffer unit configured to store a predetermined pixel and peripheral pixels neighboring the predetermined pixel in image data in a first direction and a second direction perpendicular to the first direction; and a first edge-detecting circuit configured to calculate a maximum value and a minimum value of a set of pixels selected from the peripheral pixels that have the same color as the predetermined pixel to calculate a difference value between the maximum value and the minimum value.
摘要翻译：公开了一种图像处理系统，其包括：缓冲单元，被配置为在垂直于第一方向的第一方向和第二方向上存储与图像数据中的预定像素相邻的预定像素和外围像素; 以及第一边缘检测电路，被配置为计算从与所述预定像素具有相同颜色的周边像素中选择的一组像素的最大值和最小值，以计算最大值和最小值之间的差值。

8. 发明授权

US5424969A Product-sum operation unit 失效
标题翻译：产品总和运算单元
公开(公告)号：US5424969A
公开(公告)日：1995-06-13
申请号：US13798
申请日：1993-02-05
申请人： Kenji Yamada , Kiichiro Iga , Masaru Sawada
发明人： Kenji Yamada , Kiichiro Iga , Masaru Sawada
IPC分类号： G06F7/544 , G06F7/00
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A product-sum operation unit including a multiplying unit, a pipeline register for loading a multiplication result, an adder unit for adding a summand and either an output of the pipeline register or an addend. A timing signal generating unit generates first and second timing signals (T1, T2) that are synchronized with first and second clocks (CK1, CK2). A first instruction latch loads an instruction synchronously with the first timing signal (T1) to output a first control signal. A second instruction latch loads an instruction loaded in the first instruction latch synchronously with the second timing signal (T2) to output the second control signal. A control signal selector outputs the second control signal in response to the first timing signal (T1), and also outputs the first control signal to the adder unit, in response to the second timing signal (T2).
摘要翻译：产品和运算单元，包括乘法单元，用于加载相乘结果的流水线寄存器，用于加法加法器的加法器单元和流水线寄存器的输出或加数。定时信号产生单元产生与第一和第二时钟（CK1，CK2）同步的第一和第二定时信号（T1，T2）。第一指令锁存器与第一定时信号（T1）同步地加载指令以输出第一控制信号。第二指令锁存器与第二定时信号（T2）同步地加载与第一指令锁存器相加的指令，以输出第二控制信号。控制信号选择器响应于第一定时信号（T1）输出第二控制信号，并且还响应于第二定时信号（T2）将第一控制信号输出到加法器单元。

9. 发明授权

US08023604B2 Encoded data transfer device and encoded data transferring method 有权
标题翻译：编码数据传输设备和编码数据传输方式
公开(公告)号：US08023604B2
公开(公告)日：2011-09-20
申请号：US11806890
申请日：2007-06-05
申请人： Kiichiro Iga
发明人： Kiichiro Iga
IPC分类号： H04L7/00
CPC分类号： H04N7/52 , H04N1/32448 , H04N21/23406 , H04N21/2383 , H04N21/44004
摘要： An encoded data transfer device (1) includes a JPEG compressing section (14) that converts image data to encoded data, a data buffer (15) that stores the encoded data from the JPEG compressing section (14), a stored data amount detecting section (19) that detects the stored data amount of the encoded data stored in the data buffer (15) reaching a predetermined amount DC, a data transfer section (16) that transfers the encoded data stored in the data buffer (15) to the outside in response to a result of the stored data amount detecting section (19), and a transfer data amount detecting section (27) that detects the predetermined amount DC of the encoded data being transferred from the data transferring section (16). In the data buffer (15), transfer from the JPEG compressing section (14) is inhibited in response to a result of the stored data amount detecting section (19), and transfer from the JPEG compressing section (14) is started in response to a transfer data amount detecting section (27).
摘要翻译：编码数据传送装置（1）包括将图像数据转换为编码数据的JPEG压缩部分（14），存储来自JPEG压缩部分（14）的编码数据的数据缓冲器（15），存储数据量检测部分（19），其检测存储在数据缓冲器（15）中的编码数据的存储数据量达到预定量DC;数据传送部分（16），将存储在数据缓冲器（15）中的编码数据传送到外部响应于存储数据量检测部分（19）的结果，以及检测从数据传送部分（16）传送的编码数据的预定量DC的传送数据量检测部分（27）。在数据缓冲器（15）中，响应于所存储的数据量检测部分（19）的结果，禁止从JPEG压缩部分（14）的传送，并且从JPEG压缩部分（14）的传送响应于传送数据量检测部分（27）。

10. 发明授权

US07499082B2 Distortion correction circuit for generating distortion-corrected image using data for uncorrected image 有权
标题翻译：用于使用未校正图像的数据产生失真校正图像的失真校正电路
公开(公告)号：US07499082B2
公开(公告)日：2009-03-03
申请号：US10937478
申请日：2004-09-10
申请人： Kiichiro Iga
发明人： Kiichiro Iga
IPC分类号： H04N5/228
CPC分类号： H04N5/3572
摘要： A circuit for correcting distortion produced by the lens of a digital camera when generating an image, which includes pixels. The correction circuit includes an address generation circuit for generating horizontal and vertical addresses for each pixel. A coefficient storage circuit stores a pitch correction coefficient associated with the horizontal or vertical address of each pixel. A storage circuit stores data for an image for which distortion is uncorrected in association with an address of the uncorrected image. A calculation circuit calculates the address of data of the uncorrected image corresponding to each pixel using the associated horizontal and vertical addresses and pitch correction coefficient of the horizontal or vertical address. A processing circuit reads the data of the uncorrected image from the storage circuit and generates data for a distortion-corrected image.
摘要翻译：一种用于在产生包括像素的图像时校正由数字照相机的透镜产生的失真的电路。校正电路包括用于为每个像素生成水平和垂直地址的地址产生电路。系数存储电路存储与每个像素的水平或垂直地址相关联的音调校正系数。存储电路与未校正图像的地址相关联地存储未校正失真的图像的数据。计算电路使用相关的水平和垂直地址以及水平或垂直地址的音调校正系数来计算对应于每个像素的未校正图像的数据的地址。处理电路从存储电路读取未校正图像的数据，并生成用于失真校正图像的数据。

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