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1. 发明授权

US08143656B2 High performance one-transistor DRAM cell device and manufacturing method thereof 有权
标题翻译：高性能单晶体管DRAM单元器件及其制造方法
公开(公告)号：US08143656B2
公开(公告)日：2012-03-27
申请号：US12200929
申请日：2008-08-28
申请人： Jong-Ho Lee , Ki-Heung Park
发明人： Jong-Ho Lee , Ki-Heung Park
IPC分类号： H01L29/94
CPC分类号： H01L29/7841 , G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802
摘要： Provided are a high-performance one-transistor floating-body DRAM cell device and a manufacturing method thereof. The one-transistor floating-body DRAM cell device includes: a semiconductor substrate; a gate stack which is formed on the semiconductor substrate; a control electrode which is formed on the semiconductor substrate and surrounded by the gate stack; a floating body which is formed on the control electrode that is surrounded by the gate stack; source/drain which are formed at left and right sides of the floating body; an insulating layer which insulates the source/drain from the semiconductor substrate and the control electrode; a gate insulating layer which is formed on the floating body and the source/drain; and a gate electrode which is formed on the gate insulating layer. In the cell device having a double-gate structure, charges can be stored in a non-volatile manner by the control electrodes, so that it is possible to improve a degree of integration of devices, a uniformity of characteristic, and a sensing margin.
摘要翻译：提供一种高性能单晶体体浮体DRAM单元装置及其制造方法。单晶体体浮体DRAM单元装置包括：半导体基板; 形成在所述半导体基板上的栅极叠层; 控制电极，其形成在所述半导体基板上并被所述栅极堆叠包围; 浮动体，其形成在所述控制电极上，所述浮体被所述栅极叠层包围; 在浮体的左侧和右侧形成的源极/漏极; 绝缘层，其使源极/漏极与半导体衬底和控制电极绝缘; 形成在浮体和源极/漏极上的栅极绝缘层; 以及形成在栅极绝缘层上的栅电极。在具有双栅极结构的电池装置中，可以通过控制电极以非易失性的方式存储电荷，使得可以提高器件的集成度，特性的均匀性和感测裕度。

2. 发明申请

US20120248437A1 Semiconductor Device And Test Method For Semiconductor Device 审中-公开
标题翻译：半导体器件半导体器件及测试方法
公开(公告)号：US20120248437A1
公开(公告)日：2012-10-04
申请号：US13176855
申请日：2011-07-06
申请人： Jong-Hyun Lee , Ki-Heung Park
发明人： Jong-Hyun Lee , Ki-Heung Park
IPC分类号： H01L23/52
CPC分类号： H01L22/34
摘要： A semiconductor device includes a first metal pattern formed on a first metal level. The first metal pattern has a ‘U’ shaped first curved portion. A second metal pattern is formed on the first metal level. The second metal pattern has a ‘U’ shaped second curved portion facing the first curved portion. A via structure is electrically connected to one of the first metal pattern and the second metal pattern. A third metal pattern is formed on a second metal level different from the first metal level and electrically connected to the via structure.
摘要翻译：半导体器件包括形成在第一金属层上的第一金属图案。第一金属图案具有U形的第一弯曲部分。在第一金属层上形成第二金属图案。第二金属图案具有面向第一弯曲部分的U形第二弯曲部分。通孔结构电连接到第一金属图案和第二金属图案之一。第三金属图案形成在不同于第一金属层的第二金属层上，并电连接到通孔结构。

3. 发明申请

US20100102372A1 HIGH PERFORMANCE ONE-TRANSISTOR DRAM CELL DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：高性能单晶体管DRAM器件及其制造方法
公开(公告)号：US20100102372A1
公开(公告)日：2010-04-29
申请号：US12200929
申请日：2008-08-28
申请人： Jong-Ho Lee , Ki-Heung Park
发明人： Jong-Ho Lee , Ki-Heung Park
IPC分类号： H01L27/108 , H01L21/84
CPC分类号： H01L29/7841 , G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802
摘要： Provided are a high-performance one-transistor floating-body DRAM cell device and a manufacturing method thereof. The one-transistor floating-body DRAM cell device includes: a semiconductor substrate; a gate stack which is formed on the semiconductor substrate; a control electrode which is formed on the semiconductor substrate and surrounded by the gate stack; a floating body which is formed on the control electrode that is surrounded by the gate stack; source/drain which are formed at left and right sides of the floating body; an insulating layer which insulates the source/drain from the semiconductor substrate and the control electrode; a gate insulating layer which is formed on the floating body and the source/drain; and a gate electrode which is formed on the gate insulating layer. In the cell device having a double-gate structure, charges can be stored in a non-volatile manner by the control electrodes, so that it is possible to improve a degree of integration of devices, a uniformity of characteristic, and a sensing margin.
摘要翻译：提供一种高性能单晶体体浮体DRAM单元装置及其制造方法。单晶体体浮体DRAM单元装置包括：半导体基板; 形成在所述半导体基板上的栅极叠层; 控制电极，其形成在所述半导体基板上并被所述栅极堆叠包围; 浮动体，其形成在所述控制电极上，所述浮体被所述栅极叠层包围; 在浮体的左侧和右侧形成的源极/漏极; 绝缘层，其使源极/漏极与半导体衬底和控制电极绝缘; 形成在浮体和源极/漏极上的栅极绝缘层; 以及形成在栅极绝缘层上的栅电极。在具有双栅极结构的电池装置中，可以通过控制电极以非易失性的方式存储电荷，使得可以提高器件的集成度，特性的均匀性和感测裕度。

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