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1. 发明授权

US08089820B2 Semiconductor integrated circuit and method thereof 有权
标题翻译：半导体集成电路及其方法
公开(公告)号：US08089820B2
公开(公告)日：2012-01-03
申请号：US12346225
申请日：2008-12-30
申请人： Ki-Chon Park , Jae-Hoon Cha
发明人： Ki-Chon Park , Jae-Hoon Cha
IPC分类号： G11C7/00
CPC分类号： G11C8/12
摘要： A semiconductor IC device which includes a common column signal generating block and a column strobe signal generating block. The common signal generating block can provide precolumn strobe signals by using external command signals and a first group of bank addresses among a plurality of bank addresses. The column strobe signal generating block can provide a plurality of column strobe signals to selectively activate a plurality of banks by using the precolumn strobe signals and a second group of bank addresses among the plurality of bank addresses that are not used when the precolumn strobe signals are generated.
摘要翻译：一种半导体IC器件，包括公共列信号生成块和列选通信号生成块。公共信号生成块可以通过使用外部命令信号和多个存储体地址中的第一组存储体地址组来提供预列选通信号。列选通信号产生块可以提供多个列选通信号，以通过使用前级选通信号来选择性地激活多个存储体，并且当前级选通信号是未使用的多个存储体地址之间的第二组存储体地址组时生成。

2. 发明授权

US08050119B2 Data output timing in response to read command based on whether delay locked loop is enabled/disabled in a semiconductor device 有权
标题翻译：响应于基于在半导体器件中是否允许/禁止延迟锁定环的读取命令的数据输出定时
公开(公告)号：US08050119B2
公开(公告)日：2011-11-01
申请号：US12165097
申请日：2008-06-30
申请人： Ki-Chon Park
发明人： Ki-Chon Park
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222
摘要： A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform a delay locking operation on an internal clock to output delay locked clock, and a data output control unit configured to determine a data output timing, according to whether the delay locked loop is enabled or disabled, in response to a read command.
摘要翻译：即使当延迟锁定环被禁用时，半导体存储器件也可以根据预定的数据输出定时输出数据，尽管存在系统时钟的高频率。半导体存储器件包括延迟锁定回路，被配置为对内部时钟执行延迟锁定操作以输出延迟锁定时钟;以及数据输出控制单元，被配置为根据延迟锁定环路是启用还是确定数据输出定时，禁用，响应于读命令。

3. 发明授权

US08036049B2 Semiconductor memory device including a global input/output line of a data transfer path and its surrounding circuits 有权
标题翻译：半导体存储器件包括数据传输路径的全局输入/输出线及其周围电路
公开(公告)号：US08036049B2
公开(公告)日：2011-10-11
申请号：US12469864
申请日：2009-05-21
申请人： Ki Chon Park
发明人： Ki Chon Park
IPC分类号： G11C7/10 , G11C7/22 , G11C8/00
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C8/14
摘要： A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a control signal corresponding to command and address input in read and write operation; and a repeater which selects any one of the plurality of bank groups as the control signal to control data transfer between the selected bank group and an input/output pad.
摘要翻译：一种半导体存储器件，包括数据传输路径的输入/输出线及其周围的电路，包括一个控制器，该控制器产生与读和写操作中输入的命令和地址对应的控制信号; 以及中继器，其选择多个存储体组中的任何一个作为控制信号来控制所选择的存储体组与输入/输出焊盘之间的数据传输。

4. 发明授权

US07778102B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07778102B2
公开(公告)日：2010-08-17
申请号：US12003679
申请日：2007-12-31
申请人： Jae-Hoon Cha , Ki-Chon Park
发明人： Jae-Hoon Cha , Ki-Chon Park
IPC分类号： G11C8/00
CPC分类号： G11C8/12
摘要： The present invention provides a semiconductor memory device that can reduce unnecessary current consumption, as banks not accessing data maintain an inactivation state and do not receive an input address. A semiconductor memory device includes a plurality of banks grouped into a first group and a second group; and a bank control unit for selecting one of the first group and the second group in response to a bank address to transfer an address to the selected group.
摘要翻译：本发明提供一种可以减少不必要的电流消耗的半导体存储器件，因为不存取数据的存储体保持失活状态并且不接收输入地址。半导体存储器件包括分组成第一组和第二组的多个存储体; 以及存储体控制单元，用于响应于存储体地址选择第一组和第二组中的一个，以将地址传送到所选择的组。

5. 发明授权

US07719918B2 Semiconductor memory device having input/output sense amplification circuit with reduced junction loading and circuit layout area 失效
标题翻译：半导体存储器件具有输入/输出读出放大电路，具有减少的结点负载和电路布局面积
公开(公告)号：US07719918B2
公开(公告)日：2010-05-18
申请号：US11775929
申请日：2007-07-11
申请人： Ki Chon Park
发明人： Ki Chon Park
IPC分类号： G11C8/00
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1087
摘要： A semiconductor memory device includes a plurality of sense amplifiers that amplify data transferred from each of a couple of banks and output them as amplified signals; a controller configured to determine the output states of the amplified signals outputted from each of the couple of sense amplifiers and to output driving signals corresponding to the output amplified signals; and a driver configured to receive driving signals and to drive a global input/output line in response to the driving signals, wherein the couple of sense amplifiers share the one driver.
摘要翻译：一种半导体存储器件包括：多个读出放大器，用于放大从两个存储体中的每一个传输的数据，并将其作为放大信号输出; 控制器，被配置为确定从所述两对感测放大器中的每一个输出的放大信号的输出状态，并输出与所述输出放大信号相对应的驱动信号; 以及配置成响应于驱动信号接收驱动信号和驱动全局输入/输出线的驱动器，其中所述一对感测放大器共享一个驱动器。

6. 发明申请

US20090296499A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING A GLOBAL INPUT/OUTPUT LINE OF A DATA TRANSFER PATH AND ITS SURROUNDING CIRCUITS 有权
标题翻译：半导体存储器件，包括数据传输路径及其环绕电路的全局输入/输出线
公开(公告)号：US20090296499A1
公开(公告)日：2009-12-03
申请号：US12469864
申请日：2009-05-21
申请人： Ki Chon PARK
发明人： Ki Chon PARK
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C8/14
摘要： A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a control signal corresponding to command and address input in read and write operation; and a repeater which selects any one of the plurality of bank groups as the control signal to control data transfer between the selected bank group and an input/output pad.
摘要翻译：一种半导体存储器件，包括数据传输路径的输入/输出线及其周围的电路，包括一个控制器，该控制器产生与读和写操作中输入的命令和地址对应的控制信号; 以及中继器，其选择多个存储体组中的任何一个作为控制信号来控制所选择的存储体组与输入/输出焊盘之间的数据传输。

7. 发明授权

US07843759B2 Semiconductor memory device having reduced current consumption during data mask function 有权
标题翻译：半导体存储器件在数据掩模功能期间具有降低的电流消耗
公开(公告)号：US07843759B2
公开(公告)日：2010-11-30
申请号：US12206824
申请日：2008-09-09
申请人： Ki Chon Park
发明人： Ki Chon Park
IPC分类号： G11C8/00
CPC分类号： G11C7/1006 , G11C7/1009 , G11C2207/2227
摘要： The present invention describes a semiconductor memory device having a data mask function and includes a common driving control unit for generating a common driving control signal in response to a data mask signal and a write command signal supplied to the common driving control unit. A plurality of driving units are supplied with the common driving control signal and selectively drive data according to the common driving control signal and transmit the driven data to a plurality of data lines, respectively. Accordingly, a driving and data mask operation of the plurality of driving units is controlled by the common driving control unit, which reduces current consumption and a layout area of the circuit.
摘要翻译：本发明描述了具有数据掩模功能的半导体存储器件，并且包括用于响应于提供给公共驱动控制单元的数据屏蔽信号和写入命令信号产生公共驱动控制信号的公共驱动控制单元。向多个驱动单元提供公共驱动控制信号，并根据公共驱动控制信号选择性地驱动数据，并将驱动数据分别发送到多条数据线。因此，多个驱动单元的驱动和数据掩模操作由公共驱动控制单元控制，这降低了电流消耗和电路的布局面积。

8. 发明申请

US20100067315A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD THEREOF 有权
标题翻译：半导体集成电路及其方法
公开(公告)号：US20100067315A1
公开(公告)日：2010-03-18
申请号：US12346225
申请日：2008-12-30
申请人： Ki Chon Park , Jae-Hoon Cha
发明人： Ki Chon Park , Jae-Hoon Cha
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/12
摘要： A semiconductor IC device includes a common column signal generating block providing precolumn strobe signals by using external command signals and a first group of bank addresses among a plurality of bank addresses, and a column strobe signal generating block providing a plurality of column strobe signals to selectively activate a plurality of banks by using the precolumn strobe signals and a second group of bank addresses among the plurality of bank addresses that are not used when the precolumn strobe signals are generated.
摘要翻译：半导体IC器件包括公共列信号生成块，其通过使用外部命令信号和多个存储体地址之中的第一组存储体地址组提供预置选通信号，以及列选通信号生成模块，其选择性地提供多个列选通信号通过使用前级选通信号和当生成预置选通信号时未使用的多个存储体地址之间的第二组存储体地址来激活多个存储体。

9. 发明申请

US20080239840A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING A GLOBAL INPUT/OUTPUT LINE OF A DATA TRANSFER PATH AND ITS SURROUNDING CIRCUITS 有权
标题翻译：半导体存储器件，包括数据传输路径及其环绕电路的全局输入/输出线
公开(公告)号：US20080239840A1
公开(公告)日：2008-10-02
申请号：US11778380
申请日：2007-07-16
申请人： Ki Chon PARK
发明人： Ki Chon PARK
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C8/14
摘要： A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a control signal corresponding to command and address input in read and write operation; and a repeater which selects any one of the plurality of bank groups as the control signal to control data transfer between the selected bank group and an input/output pad.
摘要翻译：一种半导体存储器件，包括数据传输路径的输入/输出线及其周围的电路，包括一个控制器，该控制器产生与读和写操作中输入的命令和地址对应的控制信号; 以及中继器，其选择多个存储体组中的任何一个作为控制信号来控制所选择的存储体组与输入/输出焊盘之间的数据传输。

10. 发明申请

US20080198680A1 SEMICONDUCTOR MEMORY DEVICE HAVING INPUT/OUTPUT SENSE AMPLIFICATION CIRCUIT WITH REDUCED JUNCTION LOADING AND CIRCUIT LAYOUT AREA 失效
标题翻译：具有输入/输出感应放大电路的半导体存储器件，具有减少的接线负载和电路布局区域
公开(公告)号：US20080198680A1
公开(公告)日：2008-08-21
申请号：US11775929
申请日：2007-07-11
申请人： Ki Chon Park
发明人： Ki Chon Park
IPC分类号： G11C8/00
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1087
摘要： A semiconductor memory device includes an input/output sense amplifier that amplifies a read data and provides it to the external, when making a read operation. The semiconductor memory device includes a plurality of sense amplifiers that amplify data transferred from each bank and output them as amplified signals; a controller that judges the output states of the amplified signals in each sense amplifier to output driving signals corresponding to the output amplified signals; and a driver that drives an global input/output line with the driving signal, wherein the first and second sense amplifiers share the one driver, making it possible to reduce ‘tAA’ and get an advantage of a layout area.
摘要翻译：半导体存储器件包括输入/输出读出放大器，其在进行读取操作时放大读取的数据并将其提供给外部。半导体存储器件包括多个读出放大器，用于放大从每个存储体传送的数据并将其作为放大信号输出; 判断每个读出放大器中放大信号的输出状态以输出与输出放大信号对应的驱动信号的控制器; 以及驱动器，其驱动具有驱动信号的全局输入/输出线，其中第一和第二读出放大器共享一个驱动器，使得可以减小“tAA”并获得布局区域的优点。

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