专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07417482B2 Adaptive voltage scaling for an electronics device 有权
标题翻译：电子设备的自适应电压调整
公开(公告)号：US07417482B2
公开(公告)日：2008-08-26
申请号：US11286087
申请日：2005-11-22
申请人： Mohamed Elgebaly , Khurram Zaka Malik , Lew G. Chua-Eoan , Seong-Ook Jung
发明人： Mohamed Elgebaly , Khurram Zaka Malik , Lew G. Chua-Eoan , Seong-Ook Jung
IPC分类号： H03H11/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Techniques for adaptively scaling voltage for a processing core are described. In one scheme, the logic speed and the wire speed for the processing core are characterized, e.g., using a ring oscillator having multiple signal paths composed of different circuit components. A target clock frequency for the processing core is determined, e.g., based on computational requirements for the core. A replicated critical path is formed based on the characterized logic speed and wire speed and the target clock frequency. This replicated critical path emulates the actual critical path in the processing core and may include different types of circuit components such as logic cells with different threshold voltages, dynamic cells, bit line cells, wires, drivers with different threshold voltages and/or fan-outs, and so on. The supply voltage for the processing core and the replicated critical path is adjusted such that both achieve the desired performance.
摘要翻译：描述了用于自适应地缩放处理核心的电压的技术。在一种方案中，处理核心的逻辑速度和线速度的特征在于，例如使用具有由不同电路部件组成的多个信号路径的环形振荡器。例如，基于对核心的计算要求来确定处理核心的目标时钟频率。基于特征逻辑速度和线速度和目标时钟频率形成复制关键路径。该复制的关键路径模拟处理核心中的实际关键路径，并且可以包括不同类型的电路组件，例如具有不同阈值电压的逻辑单元，动态单元，位线单元，电线，具有不同阈值电压的驱动器和/或扇出，等等。调整处理核心和复制关键路径的电源电压，使得两者都达到期望的性能。

2. 发明授权

US07679458B2 Ring oscillator for determining select-to-output delay of a multiplexer 有权
标题翻译：用于确定多路复用器选择输出延迟的环形振荡器
公开(公告)号：US07679458B2
公开(公告)日：2010-03-16
申请号：US11296073
申请日：2005-12-06
申请人： Khurram Zaka Malik
发明人： Khurram Zaka Malik
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , G01R31/3016 , G01R31/31727
摘要： The frequency of an oscillating signal generated by a ring oscillator is used to determine the select-to-output delay of standard cell multiplexers. The ring oscillator has no active logic elements other than an odd or even number of standard cell multiplexers. The signal path of the oscillating signal passes through the select input leads of the multiplexers of the ring oscillator. The ring oscillator can be used to characterize how signal propagation delay varies depending on the voltage supplied to the multiplexers. The lowest supply voltage at which a signal can continue to travel through the most critical circuit path of a test circuit can be modeled. In addition, the ring oscillator can be built into operational circuits to monitor timing and signal propagation delay in real time. Real time monitoring of delay enhances the benefits of adaptive voltage scaling, which is used in signal processing circuits in cell phones.
摘要翻译：由环形振荡器产生的振荡信号的频率用于确定标准单元复用器的选择输出延迟。环形振荡器没有除奇数或偶数个标准单元复用器之外的有效逻辑元件。振荡信号的信号路径通过环形振荡器的多路复用器的选择输入引线。环形振荡器可用于表征信号传播延迟如何根据提供给多路复用器的电压而变化。可以对信号可以继续行进通过测试电路的最关键电路路径的最低电源电压进行建模。此外，环形振荡器可以内置在操作电路中，以实时监控定时和信号传播延迟。延时的实时监控增强了手机信号处理电路中自适应电压缩放的好处。

3. 发明授权

US07098695B2 Dynamic-to-static logic converter 有权
标题翻译：动态到静态逻辑转换器
公开(公告)号：US07098695B2
公开(公告)日：2006-08-29
申请号：US10881535
申请日：2004-06-30
申请人： Khurram Zaka Malik
发明人： Khurram Zaka Malik
IPC分类号： H03K19/096
CPC分类号： H03K19/01855
摘要： This disclosure is directed to techniques for reducing erroneous static logic signals when logic signals change relative to a clock signal within a dynamic to static logic converter circuit. Domino logic circuits, for example, utilize dynamic logic signals evaluated relative to a clocking signal. When dynamic logic signals are evaluated, logic signals propagate within logic circuits. Dynamic to static logic converter circuits possess logic signals used to generate static logic signals that change state at well defined points in time relative to a clocking signal used by dynamic logic. Use of a delay for a clocking signal by a latch circuit utilized to capture a dynamic logic signal for conversion to a static logic signal reduces logic level changes in static logic signals during times in which dynamic logic signals may be indeterminate. Use of current limiting circuit elements associated with the latch circuit may further reduce logic level changes during these times in which dynamic logic signals may be indeterminate.
摘要翻译：本公开涉及当逻辑信号相对于动态到静态逻辑转换器电路内的时钟信号变化时减少错误静态逻辑信号的技术。例如，Domino逻辑电路利用相对于时钟信号估计的动态逻辑信号。当评估动态逻辑信号时，逻辑信号在逻辑电路内传播。动态到静态逻辑转换器电路具有用于产生静态逻辑信号的逻辑信号，所述静态逻辑信号相对于由动态逻辑使用的时钟信号在良好定义的时间点改变状态。在用于捕获用于转换为静态逻辑信号的动态逻辑信号的锁存电路中对时钟信号的延迟使用可以在动态逻辑信号可能不确定的时间期间降低静态逻辑信号中的逻辑电平变化。与锁存电路相关联的限流电路元件的使用可以在动态逻辑信号可能不确定的时间段内进一步降低逻辑电平的变化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式