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1. 发明授权

US09089677B2 Transcutaneous multimodal delivery system (TMDS) 有权
标题翻译：经皮多峰递送系统（TMDS）
公开(公告)号：US09089677B2
公开(公告)日：2015-07-28
申请号：US13358391
申请日：2012-01-25
申请人： B. Chia Soo , Kang Ting , Ben Wu , Kevin Zhang
发明人： B. Chia Soo , Kang Ting , Ben Wu , Kevin Zhang
IPC分类号： A61M37/00 , A61M9/00 , A61K9/00
CPC分类号： A61M37/0015 , A61K9/0021 , A61M2037/0023 , A61M2037/0046 , A61M2037/0053 , A61M2037/0061 , Y10T29/49826
摘要： A transcutaneous multimodal delivery device for drug delivery and the methods of making and using the same are provided.
摘要翻译：提供了用于药物递送的经皮多模式递送装置及其制造和使用方法。

2. 发明授权

US08929895B2 Apparatus and method for moving WCDMA mobile station in the manner of the least packet loss 有权
标题翻译：以最小分组丢失的方式移动WCDMA移动台的装置和方法
公开(公告)号：US08929895B2
公开(公告)日：2015-01-06
申请号：US13262258
申请日：2009-09-29
申请人： Kevin Zhang , Peter Ramle
发明人： Kevin Zhang , Peter Ramle
IPC分类号： H04W36/00 , H04W36/30 , H04W36/02
CPC分类号： H04W36/0033 , H04W36/02 , H04W36/30
摘要： A method for moving MS in the manner of the least packet loss can be divided into two steps. In the first step, when the MS is still connected to the source CN node and is running the effective loads, the MS prepares the routing information pointing at the target CN node. In the second step, the connection between the source CN node and the RAN node is released, the MS ID, the context data and the mobile information are transmitted to the target CN node. Then, a new connection between the target CN node and the RAN node is established. The step is completed synchronously and rapidly to minimize the packet loss. When establishing a new connection, the routing information transmitted to the MS before is used so that a new CN node is pointed at.
摘要翻译：以最小分组丢失的方式移动MS的方法可以分为两个步骤。在第一步，当MS仍然连接到源CN节点并且正在运行有效负载时，MS准备指向目标CN节点的路由信息。在第二步骤中，释放源CN节点和RAN节点之间的连接，将MS ID，上下文数据和移动信息发送到目标CN节点。然后，建立目标CN节点和RAN节点之间的新连接。该步骤同步快速完成，以最小化丢包。当建立新连接时，使用之前发送到MS的路由信息，以便指向新的CN节点。

3. 发明申请

US20110149667A1 REDUCED AREA MEMORY ARRAY BY USING SENSE AMPLIFIER AS WRITE DRIVER 审中-公开
标题翻译：使用感应放大器作为写驱动器减少区域内存阵列
公开(公告)号：US20110149667A1
公开(公告)日：2011-06-23
申请号：US12645645
申请日：2009-12-23
申请人： Fatih Hamzaoglu , Kevin Zhang
发明人： Fatih Hamzaoglu , Kevin Zhang
IPC分类号： G11C7/00 , G11C8/10
CPC分类号： G11C11/412 , G11C11/413
摘要： Techniques are disclosed for reducing area needed for implementing a memory array, such as SRAM arrays. The techniques may be embodied, for example, in a memory array design that includes a sense amplifier configured to operate in a reading mode for readout of memory cells and a writing mode for writing to memory cells. In addition, a common column multiplexer can be used for both read and write functions (as opposed to having separate multiplexers for reading and writing).
摘要翻译：公开了用于减少实现诸如SRAM阵列的存储器阵列所需的面积的技术。这些技术可以例如在存储器阵列设计中实现，该存储器阵列设计包括被配置为在用于读出存储器单元的读取模式下操作的读出放大器和用于写入存储器单元的写入模式。此外，公共列多路复用器可用于读和写功能（与具有用于读取和写入的单独的多路复用器相反）。

4. 发明申请

US20100165699A1 ANTIFUSE PROGRAMMABLE MEMORY ARRAY 有权
标题翻译：防伪可编程存储器阵列
公开(公告)号：US20100165699A1
公开(公告)日：2010-07-01
申请号：US12639446
申请日：2009-12-16
申请人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
发明人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： G11C17/16 , G11C17/18
摘要： Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.
摘要翻译：公开了用于有效实现诸如PROM，OTPROM和其它这样的可编程非易失性存储器的可编程存储器阵列电路架构的技术和电路。电路采用反熔丝方案，其包括存储位单元阵列，每个存储器单元包含程序设备和配置有电流路径隔离阱并用于存储存储单元状态的反熔丝元件。可以与列/行选择电路，功率选择器电路和/或读出电路结合使用的位单元配置允许高密度存储器阵列电路设计和布局。

5. 发明申请

US20100155887A1 Common plate capacitor array connections, and processes of making same 有权
标题翻译：普通板电容阵列连接及其制作工艺
公开(公告)号：US20100155887A1
公开(公告)日：2010-06-24
申请号：US12317656
申请日：2008-12-22
申请人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
发明人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/101 , H01L28/90
摘要： A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.
摘要翻译：形成用于存储电路的半导体电容器器件的工艺包括形成由第一高度的电容器单元边界隔开的第一电容器单元凹槽和第二电容器单元凹槽。该过程包括将电容器单元边界的第一高度降低到第二高度。普通的平板电容器在第一凹槽和第二凹槽之间跨过第二高度并低于第一高度的边界。

6. 发明授权

US07657767B2 Cache leakage shut-off mechanism 有权
标题翻译：缓存泄漏关闭机制
公开(公告)号：US07657767B2
公开(公告)日：2010-02-02
申请号：US11174204
申请日：2005-06-30
申请人： Stefan Rusu , Tsung-Yung Chang , Kevin Zhang , Fatih Hamzaoglu , Jonathan Shoemaker , Ming Huang
发明人： Stefan Rusu , Tsung-Yung Chang , Kevin Zhang , Fatih Hamzaoglu , Jonathan Shoemaker , Ming Huang
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/32 , G06F1/3287 , G11C11/417 , Y02D10/171
摘要： In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.
摘要翻译：在本发明的一个实施例中，提供了一种用于控制高速缓存子阵列的泄漏的技术。本文公开了其它实施例。睡眠和关闭电路连接在虚拟供应终端和第一物理供应终端之间，以便在关闭模式下禁用高速缓存子阵列时减少从高速缓存子阵列的泄漏。高速缓存子阵列连接在虚拟供电终端和第二物理供应终端之间。有源电路并联连接到睡眠和关闭电路，以使高速缓存子阵列处于正常模式，并在关闭模式下禁用高速缓存子阵列。

7. 发明申请

US20070217247A1 Shared sense amplifier for fuse cell 审中-公开
标题翻译：保险丝盒的共享放大器
公开(公告)号：US20070217247A1
公开(公告)日：2007-09-20
申请号：US11377140
申请日：2006-03-15
申请人： Zhanping Chen , Kevin Zhang , Jonathan Douglas , Praveen Mosalikanti , Gregory Taylor
发明人： Zhanping Chen , Kevin Zhang , Jonathan Douglas , Praveen Mosalikanti , Gregory Taylor
IPC分类号： G11C17/00 , G11C7/02
CPC分类号： G11C7/062 , G11C17/16
摘要： An apparatus, a method, and a system for a fuse array are disclosed herein. In some embodiments, fuse array may comprise a plurality of fuse cells and a single sense amplifier coupled to plurality of fuse cells to asynchronously sense one or more voltages output by the plurality of fuse cells, one fuse cell at a time.
摘要翻译：本文公开了一种用于熔丝阵列的装置，方法和系统。在一些实施例中，熔丝阵列可以包括多个熔丝单元和耦合到多个熔丝单元的单个读出放大器以异步地感测多个熔丝单元输出的一个或多个电压，一次一个熔丝单元。

8. 发明授权

US07230842B2 Memory cell having p-type pass device 有权
标题翻译：具有p型通过装置的存储单元
公开(公告)号：US07230842B2
公开(公告)日：2007-06-12
申请号：US11225912
申请日：2005-09-13
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Nam Sung Kim , Yibin Ye , Vivek K. De , Kevin Zhang , Bo Zheng
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Nam Sung Kim , Yibin Ye , Vivek K. De , Kevin Zhang , Bo Zheng
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , Y10S257/903
摘要： For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，一种装置包括耦合在单元电压节点和存储节点之间的第一p型装置，耦合在存储节点和参考电压节点之间的n型装置和耦合在第二p型装置之间存储节点响应于选择线上的信号到位线。衬底中的形成第一p型器件和第二p型器件的扩散区域的至少一侧基本对齐。还公开了其他实施例。

9. 发明申请

US20060067134A1 Dynamic multi-Vcc scheme for SRAM cell stability control 有权
标题翻译：用于SRAM单元稳定性控制的动态多Vcc方案
公开(公告)号：US20060067134A1
公开(公告)日：2006-03-30
申请号：US10950740
申请日：2004-09-27
申请人： Kevin Zhang , Fatih Hamzaoglu , Lin Ma
发明人： Kevin Zhang , Fatih Hamzaoglu , Lin Ma
IPC分类号： G11C7/10
CPC分类号： G11C5/14 , G11C11/413
摘要： A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first voltage when a read operation is performed, and receives a second voltage when a write operation is performed. By biasing the cell differently for the two distinct operations, a total decoupling of the read and write operations is achieved. The disclosed memory array, as well as future SRAM designs incorporating the multi-voltage capability thus avoid the conflicting requirements of read and write operations. Random single-bit failures of the memory array are reduced, due to the improvement in read stability and write margin.
摘要翻译：动态多电压存储器阵列具有不同偏置条件的SRAM单元，具体取决于单元的工作模式。所选择的SRAM单元在执行读取操作时接收第一电压，并且当执行写入操作时接收第二电压。通过针对两个不同的操作偏置单元格，可以实现读取和写入操作的完全解耦。所公开的存储器阵列以及结合多电压能力的未来SRAM设计因此避免了读写操作的冲突要求。由于读取稳定性和写入裕度的提高，存储器阵列的随机单位故障降低。

10. 发明申请

US20050041290A1 Optical interleaver, filter cell, and component design with reduced chromatic dispersion 有权
标题翻译：光学交织器，滤波器单元和具有降低的色散的组件设计
公开(公告)号：US20050041290A1
公开(公告)日：2005-02-24
申请号：US10866418
申请日：2004-06-11
申请人： Tengda Du , Kevin Zhang
发明人： Tengda Du , Kevin Zhang
IPC分类号： G02B6/34 , H04J14/02 , H04Q11/00 , G02B6/00 , G02B5/30 , G02B27/28
CPC分类号： H04J14/02 , G02B6/272 , G02B6/29302 , G02B6/29386 , H04Q11/0005 , H04Q2011/0009 , H04Q2011/0015 , H04Q2011/0016 , H04Q2011/0026 , H04Q2011/0075
摘要： An optical interleaver for use in a range of telecommunications applications including optical multiplexers/demultiplexers and optical routers. The optical device includes an optical processing loop which allows multi-stage performance characteristics to be achieved with a single physical filtration stage. Optical processing on the first leg and second legs of the loop is asymmetrical thereby improving the integrity of the optical signals by effecting complementary chromatic dispersion on the first and second legs. A fundamental filter cell within the interleaver filters optical signals propagating on each of the two legs of the optical loop which intersects the fundamental filter cell.
摘要翻译：一种用于包括光复用器/解复用器和光路由器的电信应用范围内的光交织器。光学装置包括光学处理回路，其允许通过单个物理过滤级来实现多级性能特性。在环路的第一腿部和第二腿部上的光学处理是不对称的，从而通过在第一和第二腿部上实现互补色散而提高光学信号的完整性。交织器内的基本滤波器单元滤波在与基波滤波器单元相交的光环路的两个支路上传播的光信号。

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