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    • 1. 发明申请
    • DECISION FEEDBACK EQUALIZATION WITH COMPOSITE TRELLIS SLICER
    • 决策反馈与复合TRELLIS SLICER的均衡
    • US20070140329A1
    • 2007-06-21
    • US11425602
    • 2006-06-21
    • Yuwei ZhangKevin HwangJun LuShue-Lee Chang
    • Yuwei ZhangKevin HwangJun LuShue-Lee Chang
    • H03H7/30H04B1/10
    • H04L25/03057H04L25/03267H04L2025/0349
    • A decision feedback equalizer is configured to equalize an input signal to generate a recovered output signal. Linear feed-forward filter circuitry is configured to provide a linearly filtered output signal based on the input signal. Composite trellis decoder circuitry configured to process a combined signal that is based on a combination of at least the linearly feed-forward filtered output signal and on output of linear or non-linear feedback filter circuitry, in accordance with state metrics generated by processing a composite trellis diagram relative to the combined signal, to provide a trellis-decoded output signal as input to the linear or non-linear feedback filter circuitry. The composite trellis decoder circuitry is further configured to provide a particular phase output of the combined signal, based on the state metrics, as the decoded output signal.
    • 判定反馈均衡器被配置为均衡输入信号以产生恢复的输出信号。 线性前馈滤波器电路被配置为基于输入信号提供线性滤波的输出信号。 复合网格解码器电路,被配置为处理基于至少线性前馈滤波的输出信号和线性或非线性反馈滤波器电路的输出的组合的组合信号,根据通过处理复合 网格图相对于组合信号,以提供格状解码的输出信号作为线性或非线性反馈滤波器电路的输入。 复合网格解码器电路还被配置为基于状态度量提供组合信号的特定相位输出作为解码输出信号。
    • 3. 发明授权
    • Decision feedback equalization with composite trellis slicer
    • 决策反馈均衡与复合网格切片机
    • US07680180B2
    • 2010-03-16
    • US11425602
    • 2006-06-21
    • Yuwei ZhangKevin HwangJun LuShue-Lee Chang
    • Yuwei ZhangKevin HwangJun LuShue-Lee Chang
    • H03H7/30H03H7/40H03K5/159
    • H04L25/03057H04L25/03267H04L2025/0349
    • A decision feedback equalizer is configured to equalize an input signal to generate a recovered output signal. Linear feed-forward filter circuitry is configured to provide a linearly filtered output signal based on the input signal. Composite trellis decoder circuitry configured to process a combined signal that is based on a combination of at least the linearly feed-forward filtered output signal and on output of linear or non-linear feedback filter circuitry, in accordance with state metrics generated by processing a composite trellis diagram relative to the combined signal, to provide a trellis-decoded output signal as input to the linear or non-linear feedback filter circuitry. The composite trellis decoder circuitry is further configured to provide a particular phase output of the combined signal, based on the state metrics, as the decoded output signal.
    • 判定反馈均衡器被配置为均衡输入信号以产生恢复的输出信号。 线性前馈滤波器电路被配置为基于输入信号提供线性滤波的输出信号。 复合网格解码器电路,被配置为处理基于至少线性前馈滤波的输出信号和线性或非线性反馈滤波器电路的输出的组合的组合信号,根据通过处理复合 网格图相对于组合信号,以提供格状解码的输出信号作为线性或非线性反馈滤波器电路的输入。 复合网格解码器电路还被配置为基于状态度量提供组合信号的特定相位输出作为解码输出信号。
    • 5. 发明授权
    • Low complexity multiple bits matched filter
    • 低复杂度多位匹配滤波器
    • US06426982B1
    • 2002-07-30
    • US09398939
    • 1999-09-17
    • Lin YangYan ZhongKevin Hwang
    • Lin YangYan ZhongKevin Hwang
    • H03D100
    • G06F17/15H04B1/707H04B7/195H04B2201/70707H04L27/2278H04L2027/0065
    • Method and system for efficiently and quickly forming a sequence of convolution values from an over-sampled digital signal sequence. Convolution value differences are computable from a set of digital signal values that is smaller than the original set of signal values by a factor of R, the over-sampling rate. The number of adders and the associated time delay for computation of the convolution differences are reduced by at least a factor R and by at least a factor approximately proportional to log2(R), respectively, as compared to conventional computation of a convolution value. This approach is used to estimate a time value for which the convolution attains a largest magnitude or value.
    • 用于从过采样数字信号序列有效且快速地形成卷积值序列的方法和系统。 卷积值差异可以从一组数字信号值计算,该组数字信号值小于原始信号值集合乘以R的倍数,即过采样率。 与卷积值的常规计算相比,用于计算卷积差的加法器的数量和相关联的时间延迟分别减少至少一个因子R和至少一个与log 2(R)成比例的因子。 该方法用于估计卷积达到最大幅度或值的时间值。