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1. 发明授权

US07759173B2 Methods for charge dissipation in integrated circuits 失效
标题翻译：集成电路中的电荷耗散方法
公开(公告)号：US07759173B2
公开(公告)日：2010-07-20
申请号：US12103212
申请日：2008-04-15
申请人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
发明人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
IPC分类号： H01L21/332
CPC分类号： H01L23/5226 , H01L21/743 , H01L23/5286 , H01L23/585 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
摘要翻译：在SOI衬底上集成电路中设计电荷耗散结构的方法和结构及方法。第一结构包括围绕集成电路芯片的周边的电荷耗散环以及物理和电连接到电荷消耗基座的一个或多个电荷消耗基座。 SOI衬底的硅层和体硅层通过保护环和电荷消耗基座连接。集成电路芯片的地面配电网连接到一个或多个电荷消耗基座的最上面的线段。第二种结构，用额外的电荷消耗基座元件代替电荷消除保护环。

2. 发明授权

US07408206B2 Method and structure for charge dissipation in integrated circuits 有权
标题翻译：集成电路中电荷耗散的方法和结构
公开(公告)号：US07408206B2
公开(公告)日：2008-08-05
申请号：US11164377
申请日：2005-11-21
申请人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
发明人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
IPC分类号： H01L29/017
CPC分类号： H01L23/5226 , H01L21/743 , H01L23/5286 , H01L23/585 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
摘要翻译：在SOI衬底上集成电路中设计电荷耗散结构的方法和结构及方法。第一结构包括围绕集成电路芯片的周边的电荷耗散环以及物理和电连接到电荷消耗基座的一个或多个电荷消耗基座。 SOI衬底的硅层和体硅层通过保护环和电荷消耗基座连接。集成电路芯片的地面配电网连接到一个或多个电荷消耗基座的最上面的线段。第二种结构，用额外的电荷消耗基座元件代替电荷消除保护环。

3. 发明授权

US5431772A Selective silicon nitride plasma etching process 失效
标题翻译：选择性氮化硅等离子体蚀刻工艺
公开(公告)号：US5431772A
公开(公告)日：1995-07-11
申请号：US963890
申请日：1992-10-19
申请人： Wayne T. Babie , Kenneth L. Devries , Bang C. Nguyen , Chau-Hwa J. Yang
发明人： Wayne T. Babie , Kenneth L. Devries , Bang C. Nguyen , Chau-Hwa J. Yang
IPC分类号： H01L21/00 , H01L21/311 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/67069 , H01L21/31116
摘要： A two step method of etching a silicon nitride layer carrying a surface oxygen film from a substrate in a plasma reactor employs the steps of (1) a breakthrough step of employing a plasma of oxygen free etchant gases to break through and to remove the surface oxygen containing film from the surface of the silicon nitride layer, and (2) a main step of etching the newly exposed silicon nitride with etchant gases having high selectivity with respect to the silicon oxide underlying the silicon nitride. The plasma etching can be performed while employing magnetic- enhancement of the etching. The plasma etching is performed in a plasma reactor comprising a low pressure, single wafer tool. Plasma etching is performed while employing magnetic-enhancement of the etching. The etchant gases include a halide such as a bromide and a fluoride in the breakthrough step. The etchant gases include an oxygen and bromine containing gas in the main step.
摘要翻译：在等离子体反应器中从衬底上刻蚀载有表面氧膜的氮化硅层的两步法是采用以下步骤：（1）采用无氧蚀刻剂气体的等离子体穿透并除去表面氧的突破步骤（2）主要步骤，用氮化硅下面的氧化硅对具有高选择性的蚀刻剂气蚀刻新曝光的氮化硅。可以在采用磁性增强蚀刻的同时进行等离子体蚀刻。等离子体蚀刻在包括低压单晶片工具的等离子体反应器中进行。在进行蚀刻的磁加强的同时进行等离子体蚀刻。在突破步骤中，蚀刻剂气体包括卤化物如溴化物和氟化物。在主要步骤中，蚀刻剂气体包括含氧和溴的气体。

4. 发明申请

US20080191309A1 METHODS AND STRUCTURE FOR CHARGE DISSIPATION IN INTEGRATED CIRCUITS 失效
标题翻译：集成电路充电放电的方法与结构
公开(公告)号：US20080191309A1
公开(公告)日：2008-08-14
申请号：US12103212
申请日：2008-04-15
申请人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
发明人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
IPC分类号： H01L23/58 , H01L21/762 , G06F17/50
CPC分类号： H01L23/5226 , H01L21/743 , H01L23/5286 , H01L23/585 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
摘要翻译：在SOI衬底上集成电路中设计电荷耗散结构的方法和结构及方法。第一结构包括围绕集成电路芯片的周边的电荷耗散环以及物理和电连接到电荷消耗基座的一个或多个电荷消耗基座。 SOI衬底的硅层和体硅层通过保护环和电荷消耗基座连接。集成电路芯片的地面配电网连接到一个或多个电荷消耗基座的最上面的线段。第二种结构，用额外的电荷消耗基座元件代替电荷消除保护环。

5. 发明授权

US5188704A Selective silicon nitride plasma etching 失效
标题翻译：选择性氮化硅等离子体蚀刻
公开(公告)号：US5188704A
公开(公告)日：1993-02-23
申请号：US700871
申请日：1991-05-09
申请人： Wayne T. Babie , Kenneth L. Devries , Bang C. Nguyen , Chau-Hwa J. Yang
发明人： Wayne T. Babie , Kenneth L. Devries , Bang C. Nguyen , Chau-Hwa J. Yang
IPC分类号： H01L21/311
CPC分类号： H01L21/31116
摘要： A two step method of etching a silicon nitride layer carrying a surface oxygen film from a substrate in a plasma reactor employs the steps of (1) a breakthrough step of employing a plasma of oxygen free etchant gases to break through and to remove the surface oxygen containing film from the surface of the silicon nitride layer, and (2) a main step of etching the newly exposed silicon nitride with etchant gases having high selectivity with respect to the silicon oxide underlying the silicon nitride. The plasma etching can be performed while employing magnetic-enhancement of the etching. The plasma etching is performed in a plasma reactor comprising a low pressure, single wafer tool. Plasma etching is performed while employing magnetic-enhancement of the etching. The etchant gases include a halide such as a bromide and a fluoride in the breakthrough step. The etchant gases include an oxygen and bromine containing gas in the main step.
摘要翻译：在等离子体反应器中从衬底上刻蚀载有表面氧膜的氮化硅层的两步法是采用以下步骤：（1）采用无氧蚀刻剂气体的等离子体穿透并除去表面氧的突破步骤（2）主要步骤，用氮化硅下面的氧化硅对具有高选择性的蚀刻剂气蚀刻新曝光的氮化硅。可以在使用蚀刻的磁性增强的同时进行等离子体蚀刻。等离子体蚀刻在包括低压单晶片工具的等离子体反应器中进行。在进行蚀刻的磁加强的同时进行等离子体蚀刻。在突破步骤中，蚀刻气体包括卤化物如溴化物和氟化物。在主要步骤中，蚀刻剂气体包括含氧和溴的气体。

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