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1. 再颁专利

USRE44614E1 Reliability unit for determining a reliability value for at least one bit decision 有权
标题翻译：用于确定至少一个位决定的可靠性值的可靠性单元
公开(公告)号：USRE44614E1
公开(公告)日：2013-11-26
申请号：US13530573
申请日：2012-06-22
申请人： Kelly K. Fitzpatrick , Erich F. Haratsch
发明人： Kelly K. Fitzpatrick , Erich F. Haratsch
IPC分类号： H03M13/00
CPC分类号： H03M13/4192 , H03M13/395 , H03M13/4153
摘要： A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.
摘要翻译：提供了用于确定至少一个位决定的可靠性值的可靠性单元。所公开的可靠性单元包括一个或多个功能元件，其中每个功能元件包括至少四个功能单元和至少两个寄存器，其中每个功能单元包括比较器和多路复用器，并且其中比较器的输出和等效位控制多路复用器。通常，可靠性单元确定与通过多步网格的最大似然路径相关联的位决定的可靠性值。

2. 发明授权

US08862957B2 Symbol selective scaling with parity forcing 有权
标题翻译：带有奇偶校验强制的符号选择性缩放
公开(公告)号：US08862957B2
公开(公告)日：2014-10-14
申请号：US13560737
申请日：2012-07-27
申请人： Weijun Tan , Shaohua Yang , Kelly K. Fitzpatrick , Xuebin Wu , Fan Zhang
发明人： Weijun Tan , Shaohua Yang , Kelly K. Fitzpatrick , Xuebin Wu , Fan Zhang
IPC分类号： H03M13/00 , H03M13/05 , H04B15/00
CPC分类号： H03M13/05 , G06F11/1076 , G11B20/1833 , H03M13/1111 , H03M13/1128 , H03M13/6331 , H03M13/6343 , H03M13/658 , H04B15/00
摘要： The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.
摘要翻译：本发明涉及用于数据处理的系统和方法，更具体地涉及具有与奇偶校验强迫交互的符号选择性缩放的数据处理系统的系统和方法。

3. 发明授权

US06417788B1 High rate runlength limited codes for 10-bit ECC symbols 有权
标题翻译： 10位ECC符号的高速率游程限制码
公开(公告)号：US06417788B1
公开(公告)日：2002-07-09
申请号：US09803401
申请日：2001-03-09
申请人： Peter McEwen , Kelly K Fitzpatrick , Bahjat M. Zafer
发明人： Peter McEwen , Kelly K Fitzpatrick , Bahjat M. Zafer
IPC分类号： H03M700
CPC分类号： G11B5/09 , H03M7/46
摘要： A methodology for designing an implementing high rate RLL codes is optimized for application to 10-bit ECC symbols, and provides rate 20/21, rate 50/51, rate 90/91 and other modulation code rates for use in magnetic recording channels. A relatively small subcode encoding—one easy to implement—is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.
摘要翻译：用于设计实现的高速率RLL码的方法被优化用于应用于10位ECC符号，并提供用于磁记录通道的速率20/21，速率50/51，速率90/91和其他调制码率。一个易于实现的相对较小的子代码编码被应用到输入流的一部分，并且所得到的基本码字被分割成半字节，其进而在未经编码的ECC符号之间进行交织。子代码字半字节上的代码约束取决于相邻未编码符号的值。所得到的代码提供了出色的密度和误差传播性能。

4. 发明授权

US06310739B1 Method and system for detection recording media defacts 失效
标题翻译：用于检测记录媒体的方法和系统
公开(公告)号：US06310739B1
公开(公告)日：2001-10-30
申请号：US09283351
申请日：1999-03-31
申请人： Peter A. McEwen , Bahjat Zafer , Kelly K. Fitzpatrick , Ke Han , Steve Aronson , Kevin Fisher
发明人： Peter A. McEwen , Bahjat Zafer , Kelly K. Fitzpatrick , Ke Han , Steve Aronson , Kevin Fisher
IPC分类号： G11B502
CPC分类号： G11B27/36 , G01R33/1207 , G11B5/00 , G11B5/012 , G11B33/10 , G11B2220/20
摘要： A discrete-time filtering method for identifying defects in a magnetic medium, comprising the steps of: reading data signals from at least a portion of the medium; sampling the data signals to generate discrete time sample data; processing the sample data in a discrete time filter to detect deviation of the signal corresponding to media defects; and comparing the deviation of the signal to one or more threshold values to identify corresponding defect types on the recording medium. The filter can be configured to have an impulse response substantially matched to deviation of the signal corresponding to media defects.
摘要翻译：一种用于识别磁介质中的缺陷的离散时间滤波方法，包括以下步骤：从介质的至少一部分读取数据信号; 对数据信号进行采样以产生离散时间采样数据; 在离散时间滤波器中处理样本数据以检测对应于介质缺陷的信号的偏差; 以及将信号的偏差与一个或多个阈值进行比较，以识别记录介质上的相应缺陷类型。滤波器可以被配置为具有与对应于介质缺陷的信号的偏差基本匹配的脉冲响应。

5. 发明授权

US5949357A Time-varying maximum-transition-run codes for data channels 失效
标题翻译：数据通道的时变最大过渡运行代码
公开(公告)号：US5949357A
公开(公告)日：1999-09-07
申请号：US782182
申请日：1997-01-13
申请人： Kelly K. Fitzpatrick , Cory Modlin
发明人： Kelly K. Fitzpatrick , Cory Modlin
IPC分类号： G11B20/10 , G11B20/14 , H03M5/14 , H03M7/00
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/1426 , H03M5/145 , G11B2020/1434
摘要： A data channel, such as a magnetic recording/playback channel implements a time-varying maximum-transition-run code such that the code allows three consecutive transitions while it removes a dominant plus-minus-plus error-event and does not permit of four or more consecutive transitions.
摘要翻译：诸如磁记录/重放通道的数据通道实现时变最大过渡运行代码，使得代码允许三个连续的转换，同时它消除了主要的加 - 减加错误事件，并且不允许四或更多的连续过渡。

6. 发明申请

US20140032989A1 Symbol Selective Scaling With Parity Forcing 有权
标题翻译：符号选择性缩放与奇偶逼迫
公开(公告)号：US20140032989A1
公开(公告)日：2014-01-30
申请号：US13560737
申请日：2012-07-27
申请人： Weijun Tan , Shaohua Yang , Kelly K. Fitzpatrick , Xuebin Wu , Fan Zhang
发明人： Weijun Tan , Shaohua Yang , Kelly K. Fitzpatrick , Xuebin Wu , Fan Zhang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/05 , G06F11/1076 , G11B20/1833 , H03M13/1111 , H03M13/1128 , H03M13/6331 , H03M13/6343 , H03M13/658 , H04B15/00
摘要： The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.
摘要翻译：本发明涉及用于数据处理的系统和方法，更具体地涉及具有与奇偶校验强迫交互的符号选择性缩放的数据处理系统的系统和方法。

7. 发明授权

US5689532A Reduced complexity EPR4 post-processor for sampled data detection 失效
标题翻译：降低复杂度EPR4后处理器，用于采样数据检测
公开(公告)号：US5689532A
公开(公告)日：1997-11-18
申请号：US655358
申请日：1996-05-24
申请人： Kelly K. Fitzpatrick
发明人： Kelly K. Fitzpatrick
IPC分类号： G11B5/09 , G11B20/10 , G11B20/18 , H03M13/23 , H04L25/497 , H03D1/00
CPC分类号： G11B20/10074 , G11B20/10009 , H04L25/497
摘要： An EPR4 detector comprises a PR4 Viterbi detector and an EPR4 post-processor for improving estimated output sequence at an output of the PR4 Viterbi. The PR4 Viterbi detector produces digital estimates of coded digital information values into the channel in accordance with a path through a PR4 trellis and produces other path information relating to other paths through the PR4 trellis. The EPR4 post-processor has a PR4 path storage circuit for receiving and storing the estimated sequence of coded digital information values which corresponds to a PR4 path through a sequence of states of an EPR4 trellis; an error-event selection circuit for receiving the other path information from the PR4 Viterbi detector for generating non-overlapping error-events from a set of error-events deviating from the PR4 path through the EPR4 trellis stored in the PR4 path storage circuit, and a path correction circuit connected to the PR4 path storage circuit and to the error-event selection circuit for correcting non-overlapping error-events deviating from the PR4 path through the EPR4 trellis, and for putting out a corrected estimated sequence of coded digital information values. An EPR4 detection method is also disclosed.
摘要翻译： EPR4检测器包括PR4维特比检测器和用于改善PR4维特比输出端的估计输出序列的EPR4后处理器。 PR4维特比检测器根据通过PR4格网的路径产生编码数字信息值到信道中的数字估计，并产生与通过PR4网格的其他路径有关的其他路径信息。 EPR4后处理器具有PR4路径存储电路，用于通过EPR4网格的状态序列来接收和存储对应于PR4路径的编码数字信息值的估计序列; 错误事件选择电路，用于从PR4维特比检测器接收另一路径信息，用于通过PR4路径通过存储在PR4路径存储电路中的EPR4网格偏离PR4路径的错误事件组生成非重叠的错误事件;以及连接到PR4路径存储电路和误差事件选择电路的路径校正电路，用于校正偏离通过EPR4网格的PR4路径的非重叠的错误事件，并且用于输出校正的编码的数字信息值的估计序列。还公开了EPR4检测方法。

8. 发明授权

US08711984B2 Methods and apparatus for map detection with reduced complexity 有权
标题翻译：降低复杂度的地图检测方法和装置
公开(公告)号：US08711984B2
公开(公告)日：2014-04-29
申请号：US12017765
申请日：2008-01-22
申请人： Kelly K. Fitzpatrick , Erich F. Haratsch
发明人： Kelly K. Fitzpatrick , Erich F. Haratsch
IPC分类号： H04L27/06
CPC分类号： G11B5/09 , H03M13/3905 , H03M13/395 , H03M13/6343 , H03M13/6502 , H04L1/0055 , H04L1/0066
摘要： Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft output channel detector is provided that operates at a rate of 1/N and detects N bits per 1/N-rate clock cycle. The channel detector comprises a plurality, D, of MAP detectors operating in parallel, wherein each of the MAP detectors generates N/D log-likelihood ratio values per 1/N-rate clock cycle and wherein at least one of the plurality of MAP detectors constrains each of the bits. The log-likelihood ratio values can be merged to form an output sequence. A single MAP detector is also provided that comprises a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ different trellis structures.
摘要翻译：提供了高速，低功耗，高性能通道检测的方法和装置。提供了以1 / N的速率操作的软输出通道检测器，并且每1 / N速率时钟周期检测N位。信道检测器包括并行操作的多个MAP检测器，其中每个MAP检测器每1 / N速率时钟周期产生N / D对数似然比值，并且其中多个MAP检测器中的至少一个限制每个位。对数似然比值可以合并形成输出序列。还提供单个MAP检测器，其包括用于计算前向状态度量的前向检测器; 用于计算后向状态度量的反向检测器; 以及用于计算当前分支量度的当前分支检测器，其中所述正向检测器，所述后向检测器和所述当前支路检测器中的至少两个采用不同的格状结构。

9. 发明授权

US06249398B1 Class of fixed partial response targets in a PRML sampled data detection channel 失效
标题翻译： PRML采样数据检测通道中固定部分响应目标的类别
公开(公告)号：US06249398B1
公开(公告)日：2001-06-19
申请号：US09034933
申请日：1998-03-04
申请人： Kevin Fisher , Kelly K. Fitzpatrick , Cory Modlin , Ara Patapoutian , Jeffrey L. Sonntag , Necip Sayiner
发明人： Kevin Fisher , Kelly K. Fitzpatrick , Cory Modlin , Ara Patapoutian , Jeffrey L. Sonntag , Necip Sayiner
IPC分类号： G11B5035
CPC分类号： G11B20/10055 , G11B5/09 , G11B20/10009 , G11B20/10037 , G11B20/10296
摘要： A new class of fixed partial response targets are disclosed for use in a PRML magnetic medium read channel. The preferred embodiment exhibits an equalization response characterized by the polynomial 7+4*D−4*D2−5*D3−2*D4, where D represents the unit delay operator. This read channel target provides improved matching to the inherent magnetic channel over the known canonical class of targets (1−D)(1+D){circumflex over ( )}N, and thereby reduces equalization losses. The improved spectral matching reduces amplification of noise in the channel, thereby reducing bit-error-rates. The new class of targets also exhibits a spectral null at DC, reducing problems for offset cancellation circuitry and making the disk drive less sensitive to thermal asperities. It also exhibits a spectral depression rather than a spectral null at the Nyquist frequency, making quasi-catastrophic error sequences virtually impossible. The new class of target simplifies coding and allows RLL code ratios that approach unity, improving effective recording densities, while significantly reducing BER.
摘要翻译：公开了一类新的固定部分响应目标，用于PRML磁介质读取通道。优选实施例表现出由多项式7 + 4 * D-4 * D2-5 * D3-2 * D4表征的均衡响应，其中D表示单位延迟算子。这个读通道目标在已知的典型目标类别（1-D）（1 + D）{circumflex over（）} N上提供与固有磁通道的改进的匹配，从而减少均衡损失。改进的频谱匹配减少了信道中噪声的放大，从而降低了误码率。新类别的目标还在DC处表现出光谱零点，减少偏移消除电路的问题，并使磁盘驱动器对热凹凸不敏感。在奈奎斯特频率下，它也表现出光谱抑制而不是光谱零点，使得准灾难性误差序列实际上是不可能的。新类别的目标简化了编码，并允许RLL代码比率达到统一，提高了有效的记录密度，同时显着降低了BER。

10. 发明申请

US20090185643A1 Methods and Apparatus for Map Detection with Reduced Complexity 有权
标题翻译：降低复杂度的地图检测方法与装置
公开(公告)号：US20090185643A1
公开(公告)日：2009-07-23
申请号：US12017765
申请日：2008-01-22
申请人： Kelly K. Fitzpatrick , Erich F. Haratsch
发明人： Kelly K. Fitzpatrick , Erich F. Haratsch
IPC分类号： H04L27/06
CPC分类号： G11B5/09 , H03M13/3905 , H03M13/395 , H03M13/6343 , H03M13/6502 , H04L1/0055 , H04L1/0066
摘要： Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft output channel detector is provided that operates at a rate of 1/N and detects N bits per 1/N-rate clock cycle. The channel detector comprises a plurality, D, of MAP detectors operating in parallel, wherein each of the MAP detectors generates N/D log-likelihood ratio values per 1/N-rate clock cycle and wherein at least one of the plurality of MAP detectors constrains each of the bits. The log-likelihood ratio values can be merged to form an output sequence. A single MAP detector is also provided that comprises a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ different trellis structures.
摘要翻译：提供了高速，低功耗，高性能通道检测的方法和装置。提供了以1 / N的速率操作的软输出通道检测器，并且每1 / N速率时钟周期检测N位。信道检测器包括并行操作的多个MAP检测器，其中每个MAP检测器每1 / N速率时钟周期产生N / D对数似然比值，并且其中多个MAP检测器中的至少一个限制每个位。对数似然比值可以合并形成输出序列。还提供单个MAP检测器，其包括用于计算前向状态度量的前向检测器; 用于计算后向状态度量的反向检测器; 以及用于计算当前分支量度的当前分支检测器，其中所述正向检测器，所述后向检测器和所述当前支路检测器中的至少两个采用不同的格状结构。

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