专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07271490B2 Semiconductor device having dummy wiring layers and a method for manufacturing the same 有权
标题翻译：具有虚拟布线层的半导体器件及其制造方法
公开(公告)号：US07271490B2
公开(公告)日：2007-09-18
申请号：US10999290
申请日：2004-11-29
申请人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
发明人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L27/0207 , G06F17/5077 , G06F17/5081 , H01L21/76816 , H01L21/76819 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
摘要翻译：半导体器件具有设置在与第一布线层30相同的层上的第一布线层30和多个伪布线层32。半导体器件限定行方向，并且在沿着行方向的方向上延伸的第一虚拟线性线L 1。行方向和第一虚拟线性线L 1限定为2-40度的角度，虚拟布线层32以位于第一假想线状线L 1上的方式配置。半导体器件还限定垂直于行方向的列方向，以及在沿着列方向的方向上延伸的第二虚拟线性线L 2。列方向和第二虚拟线性线L 2限定为2-40度的角度，并且虚设布线层32以位于第二虚拟线性线L 2上的方式设置。

2. 发明授权

US06605852B2 Semiconductor device and method for manufacturing the same including forming a plurality of dummy convex regions on a matrix with a virtual linear line defining an angle 有权
标题翻译：半导体器件及其制造方法，包括在矩阵上形成多个虚拟凸起区域，其中虚拟线性线限定角度
公开(公告)号：US06605852B2
公开(公告)日：2003-08-12
申请号：US09761963
申请日：2001-01-17
申请人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
发明人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
IPC分类号： H01L3100
CPC分类号： H01L21/76229
摘要： A semiconductor device includes a silicon substrate 10 having a trench isolation region 24. A plurality of dummy convex regions 32 are formed in the trench isolation region 24. The trench isolation region 24 defines a row direction and a column direction. Also, the trench isolation region 24 define first virtual linear lines L1 that extend in a direction traversing the row direction and second virtual linear lines L2 that extend in a direction traversing the column direction. The first virtual linear lines L1 and the row direction define an angle of 2-40 degree, and the second virtual linear lines L2 and the column direction define an angle of 2-40 degree. The dummy convex regions 32 are disposed on the first virtual linear lines L1 and the second virtual linear lines L2.
摘要翻译：半导体器件包括具有沟槽隔离区域24的硅衬底10.在沟槽隔离区域24中形成多个伪凸区域32.沟槽隔离区域24限定行方向和列方向。此外，沟槽隔离区域24限定在横过行方向的方向上延伸的第一虚拟线性线L1和沿着列方向的方向延伸的第二虚拟线性线L2。第一虚拟线性线L1和行方向限定2-40度的角度，并且第二虚拟线性线L2和列方向限定2-40度的角度。虚拟凸区域32设置在第一虚拟线性线L1和第二假想直线L2上。

3. 发明授权

US08418114B2 Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium 有权
公开(公告)号：US08418114B2
公开(公告)日：2013-04-09
申请号：US13485165
申请日：2012-05-31
申请人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
发明人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
IPC分类号： G06F17/50 , H01L21/4763
CPC分类号： H01L27/0207 , G06F17/5077 , G06F17/5081 , H01L21/76816 , H01L21/76819 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.

4. 发明申请

US20110239170A1 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM 有权
标题翻译：半导体器件，其制造方法，用于生成掩蔽数据的方法，掩蔽和计算机可读记录介质
公开(公告)号：US20110239170A1
公开(公告)日：2011-09-29
申请号：US13153764
申请日：2011-06-06
申请人： Katsumi MORI , Kei KAWAHARA , Yoshikazu KASUYA
发明人： Katsumi MORI , Kei KAWAHARA , Yoshikazu KASUYA
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5077 , G06F17/5081 , H01L21/76816 , H01L21/76819 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
摘要翻译：半导体器件具有设置在与第一布线层30相同的层上的第一布线层30和多个伪布线层32.半导体器件限定行方向，并且沿着穿过第一布线层30的方向延伸的第一虚拟线性线L1 行方向。行方向和第一虚拟线性线L1限定2-40度的角度，并且虚设布线层32以位于第一虚拟线性线L1上的方式设置。半导体器件还限定垂直于行方向的列方向，以及在沿着列方向的方向上延伸的第二虚拟线性线L2。列方向和第二虚拟线性线L2限定2-40度的角度，并且虚设布线层32以位于第二虚拟线性线L2上的方式设置。

5. 发明授权

US07802224B2 Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium 有权
标题翻译：半导体装置及其制造方法，掩模数据生成方法，掩模和计算机可读记录介质
公开(公告)号：US07802224B2
公开(公告)日：2010-09-21
申请号：US11893228
申请日：2007-08-15
申请人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
发明人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5077 , G06F17/5081 , H01L21/76816 , H01L21/76819 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
摘要翻译：半导体器件具有设置在与第一布线层30相同的层上的第一布线层30和多个伪布线层32.半导体器件限定行方向，并且沿着穿过第一布线层30的方向延伸的第一虚拟线性线L1 行方向。行方向和第一虚拟线性线L1限定2-40度的角度，并且虚设布线层32以位于第一虚拟线性线L1上的方式设置。半导体器件还限定垂直于行方向的列方向，以及在沿着列方向的方向上延伸的第二虚拟线性线L2。列方向和第二虚拟线性线L2限定2-40度的角度，并且虚设布线层32以位于第二虚拟线性线L2上的方式设置。

6. 发明授权

US06437455B1 Semiconductor device having gate-gate, drain-drain, and drain-gate connecting layers and method of fabricating the same 有权
公开(公告)号：US06437455B1
公开(公告)日：2002-08-20
申请号：US09758390
申请日：2001-01-12
申请人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
发明人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
IPC分类号： H01L2711
摘要： A semiconductor memory device comprising first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers. The first and second gate-gate connecting layers respectively connect a gate of a driver transistor to a gate of a load transistor. The first and second drain-drain connecting layers are formed over a first interlayer dielectric and have a refractory metal nitride layer. The first and second drain-drain connecting layers respectively connect a drain of the driver transistor to a drain of the load transistor. The first and second drain-gate connecting layers are formed over a second interlayer dielectric, and respectively connect the first drain-drain connecting layer to the second gate-gate connecting layer, and the second drain-drain connecting layer to the first gate-gate connecting layer.

7. 发明授权

US06404023B1 Semiconductor device having gate-gate, drain-drain, and drain-gate connecting layers and method of fabricating the same 有权
标题翻译：具有栅极栅极，漏极 - 漏极和漏极 - 栅极连接层的半导体器件及其制造方法
公开(公告)号：US06404023B1
公开(公告)日：2002-06-11
申请号：US09758388
申请日：2001-01-12
申请人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
发明人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： A semiconductor device comprising a peripheral circuit portion and a memory cell portion including a plurality of memory cells. Each memory cell has first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers. The first and second gate-gate connecting layers respectively connect the gates of driver transistors to the gates of load transistors. The first and second drain-drain connecting layers are formed over a first interlayer dielectric and respectively connect the drains of driver transistors to the drains of load transistors. The first and second drain-gate connecting layers are formed over a second interlayer dielectric and respectively connect the first drain-drain connecting layer to the second gate-gate connecting layer and the second drain-drain connecting layer to the first gate-gate connecting layer.
摘要翻译：一种半导体器件，包括外围电路部分和包括多个存储单元的存储单元部分。每个存储单元具有第一和第二栅极栅极连接层，第一和第二漏极 - 漏极连接层以及第一和第二漏极 - 栅极连接层。第一和第二栅极连接层分别将驱动晶体管的栅极连接到负载晶体管的栅极。第一和第二漏极 - 漏极连接层形成在第一层间电介质上，并分别将驱动晶体管的漏极连接到负载晶体管的漏极。第一和第二漏极 - 栅极连接层形成在第二层间电介质上，并且将第一漏极 - 漏极连接层与第二栅极 - 栅极连接层和第二漏极 - 漏极连接层分别连接到第一栅极 - 栅极连接层。

8. 发明申请

US20120246603A1 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM 有权
标题翻译：半导体器件，其制造方法，用于生成掩蔽数据的方法，掩蔽和计算机可读记录介质
公开(公告)号：US20120246603A1
公开(公告)日：2012-09-27
申请号：US13485165
申请日：2012-05-31
申请人： Katsumi MORI , Kei KAWAHARA , Yoshikazu KASUYA
发明人： Katsumi MORI , Kei KAWAHARA , Yoshikazu KASUYA
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5077 , G06F17/5081 , H01L21/76816 , H01L21/76819 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
摘要翻译：半导体器件具有设置在与第一布线层相同的层上的第一布线层和多个伪布线层。半导体器件限定行方向，并且沿着穿过行方向的方向延伸的第一虚拟线性线。行方向和第一虚拟线性线限定2-40度的角度，并且虚设布线层以设置在第一虚拟线性线上的方式设置。半导体器件还定义垂直于行方向的列方向，以及在沿着列方向的方向上延伸的第二虚拟线性线。列方向和第二虚拟线性线限定2-40度的角度，并且虚拟布线层以位于第二虚拟线性线上的方式设置。

9. 发明申请

US20080045000A1 Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium 有权
标题翻译：半导体装置及其制造方法，掩模数据生成方法，掩模和计算机可读记录介质
公开(公告)号：US20080045000A1
公开(公告)日：2008-02-21
申请号：US11893228
申请日：2007-08-15
申请人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
发明人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
IPC分类号： H01L21/4763
CPC分类号： H01L27/0207 , G06F17/5077 , G06F17/5081 , H01L21/76816 , H01L21/76819 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
摘要翻译：半导体器件具有设置在与第一布线层30相同的层上的第一布线层30和多个伪布线层32。半导体器件限定行方向，并且在沿着行方向的方向上延伸的第一虚拟线性线L 1。行方向和第一虚拟线性线L 1限定为2-40度的角度，虚拟布线层32以位于第一假想线状线L 1上的方式配置。半导体器件还限定垂直于行方向的列方向，以及在沿着列方向的方向上延伸的第二虚拟线性线L 2。列方向和第二虚拟线性线L 2限定为2-40度的角度，并且虚设布线层32以位于第二虚拟线性线L 2上的方式设置。

10. 发明授权

US08214776B2 Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium 有权
标题翻译：半导体装置及其制造方法，掩模数据生成方法，掩模和计算机可读记录介质
公开(公告)号：US08214776B2
公开(公告)日：2012-07-03
申请号：US13153764
申请日：2011-06-06
申请人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
发明人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
IPC分类号： G06F17/50 , G06F9/455 , H01L31/00 , H01L27/088
CPC分类号： H01L27/0207 , G06F17/5077 , G06F17/5081 , H01L21/76816 , H01L21/76819 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
摘要翻译：半导体器件具有设置在与第一布线层30相同的层上的第一布线层30和多个伪布线层32.半导体器件限定行方向，并且沿着穿过第一布线层30的方向延伸的第一虚拟线性线L1 行方向。行方向和第一虚拟线性线L1限定2-40度的角度，并且虚设布线层32以位于第一虚拟线性线L1上的方式设置。半导体器件还限定垂直于行方向的列方向，以及在沿着列方向的方向上延伸的第二虚拟线性线L2。列方向和第二虚拟线性线L2限定2-40度的角度，并且虚设布线层32以位于第二虚拟线性线L2上的方式设置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式