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1. 发明授权

US07577540B2 Re-configurable embedded core test protocol for system-on-chips (SOC) and circuit boards 失效
标题翻译：可重配置的嵌入式核心测试协议（SOC）和电路板
公开(公告)号：US07577540B2
公开(公告)日：2009-08-18
申请号：US10108476
申请日：2002-03-29
申请人： Seongmoon Wang , Srimat T. Chakradhar , Kedarnath J. Balakrishnan
发明人： Seongmoon Wang , Srimat T. Chakradhar , Kedarnath J. Balakrishnan
IPC分类号： G01R31/317 , G06F11/26
CPC分类号： G06F11/2242
摘要： A test system for a circuit board , wherein the circuit board has a plurality of cores such that at least one of the plurality of cores is adapted to use a test protocol independent of a communication fabric used in the circuit board. A system-on-chip (SOC) with an embedded test protocol architecture, the SOC comprising at least one embedded core, a communication fabric that connects at least one embedded core, at least one test server; and at least one test client connected to said at least one embedded core and connected to the communication fabric.
摘要翻译：一种用于电路板的测试系统，其中所述电路板具有多个芯，使得所述多个芯中的至少一个芯适于使用独立于所述电路板中使用的通信结构的测试协议。一种具有嵌入式测试协议架构的片上系统（SOC），所述SOC包括至少一个嵌入式核心，连接至少一个嵌入式核心的通信结构，至少一个测试服务器; 以及连接到所述至少一个嵌入式核心并连接到所述通信结构的至少一个测试客户端。

2. 发明申请

US20120159274A1 APPARATUS TO FACILITATE BUILT-IN SELF-TEST DATA COLLECTION 审中-公开
标题翻译：装备内置自检数据收集装置
公开(公告)号：US20120159274A1
公开(公告)日：2012-06-21
申请号：US12975342
申请日：2010-12-21
申请人： Kedarnath J. Balakrishnan , Grady Giles , Tim Wood , Eswar Vadlamani
发明人： Kedarnath J. Balakrishnan , Grady Giles , Tim Wood , Eswar Vadlamani
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31703 , G01R31/3187
摘要： Techniques are disclosed relating to testing logic in integrated circuits using an external test tool. In one embodiment, an integrated circuit includes a logic unit and a self-test unit. The self-test unit is configured to receive an expected signature value that corresponds to an expected output value of the logic unit, and to compare the expected signature value and an actual signature value generated from an actual output value from the logic unit. In some embodiments, the integrated circuit further includes a pseudo-random pattern generator configured to provide an input value to the logic unit, and the logic unit is configured to generate the actual output value based on the provided input value. In some embodiments, the integrated circuit further includes a multiple-input signature register (MISR) configured to generate the actual signature value based on the actual output value and a seed value.
摘要翻译：公开了使用外部测试工具的集成电路中的测试逻辑的技术。在一个实施例中，集成电路包括逻辑单元和自检单元。自检单元被配置为接收对应于逻辑单元的预期输出值的预期签名值，并且将预期签名值与从逻辑单元的实际输出值生成的实际签名值进行比较。在一些实施例中，集成电路还包括被配置为向逻辑单元提供输入值的伪随机模式发生器，并且逻辑单元被配置为基于所提供的输入值生成实际输出值。在一些实施例中，集成电路还包括被配置为基于实际输出值和种子值生成实际签名值的多输入签名寄存器（MISR）。

3. 发明授权

US07610527B2 Test output compaction with improved blocking of unknown values 失效
标题翻译：测试输出压实，改进阻塞未知值
公开(公告)号：US07610527B2
公开(公告)日：2009-10-27
申请号：US11276771
申请日：2006-03-14
申请人： Seongmoon Wang , Kedarnath J Balakrishnan , Srimat T Chakradhar
发明人： Seongmoon Wang , Kedarnath J Balakrishnan , Srimat T Chakradhar
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G01R31/318335 , G01R31/3181
摘要： Implementations of the present principles are directed to test output compaction arrangements and a methods of generating control patterns for unknown blocking. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.
摘要翻译：本原理的实现涉及测试输出压缩布置以及产生未知阻塞的控制模式的方法。当使用线性反馈移位寄存器（LFSR）重新进给确定控制数据量和LFSR大小时，控制模式中的指定位优选地以使得跨越测试模式平衡控制模式中的指定位的数目的方式来组织。

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