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1. 发明授权

US07346412B2 Manufacturing method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07346412B2
公开(公告)日：2008-03-18
申请号：US10578723
申请日：2004-10-26
申请人： Kazuyuki Tokorozuki , Toshihiro Nakajima , Yoshiyuki Miyamoto , Yoshio Fukayama
发明人： Kazuyuki Tokorozuki , Toshihiro Nakajima , Yoshiyuki Miyamoto , Yoshio Fukayama
IPC分类号： G06F19/00 , G06F15/00 , G06F17/30 , G05B13/02
CPC分类号： H01L22/20 , G05B2219/32179 , H01L21/67276 , H01L2924/0002 , Y02P90/22 , Y10S707/99931 , H01L2924/00
摘要： The invention intends to provide a manufacturing method of a semiconductor integrated circuit device, which can detect an off-specification faulty wafer in real time. An abnormality detection server stores apparatus log data outputted from semiconductor manufacturing apparatus that processes a semiconductor wafer in an apparatus log data memory. Thereafter, in a lot end signal receiver, when a lot end signal outputted from the semiconductor manufacturing apparatus is received, an abnormal data detector, after referencing an abnormality detection condition setting file stored in a first detection condition memory, based on the referenced content, judges whether there are abnormal data in the apparatus log data stored in the apparatus log data memory or not. Upon detecting an abnormality, a detection result is outputted to an engineer PC and an operator terminal unit.
摘要翻译：本发明意图提供一种半导体集成电路器件的制造方法，其可以实时检测不合格的故障晶片。异常检测服务器存储从设备日志数据存储器中处理半导体晶片的半导体制造装置输出的装置对数据。此后，在多个终端信号接收机中，当接收到从半导体制造装置输出的批结束信号时，异常数据检测器在参考存储在第一检测条件存储器中的异常检测条件设置文件之后，基于所引用的内容，判断在装置日志数据存储器中存储的装置记录数据中是否存在异常数据。当检测到异常时，将检测结果输出到工程师PC和操作终端单元。

2. 发明申请

US20070097763A1 Manufacturing method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20070097763A1
公开(公告)日：2007-05-03
申请号：US10578723
申请日：2004-10-26
申请人： Kazuyuki Tokorozuki , Toshihiro Nakajima , Yoshiyuki Miyamoto , Yoshio Fukayama
发明人： Kazuyuki Tokorozuki , Toshihiro Nakajima , Yoshiyuki Miyamoto , Yoshio Fukayama
IPC分类号： G11C29/00
CPC分类号： H01L22/20 , G05B2219/32179 , H01L21/67276 , H01L2924/0002 , Y02P90/22 , Y10S707/99931 , H01L2924/00
摘要： The invention intends to provide a manufacturing method of a semiconductor integrated circuit device, which can detect an off-specification faulty wafer in real time. An abnormality detection server stores apparatus log data outputted from semiconductor manufacturing apparatus that processes a semiconductor wafer in an apparatus log data memory. Thereafter, in a lot end signal receiver, when a lot end signal outputted from the semiconductor manufacturing apparatus is received, an abnormal data detector, after referencing an abnormality detection condition setting file stored in a first detection condition memory, based on the referenced content, judges whether there are abnormal data in the apparatus log data stored in the apparatus log data memory or not. Upon detecting an abnormality, a detection result is outputted to an engineer PC and an operator terminal unit.
摘要翻译：本发明意图提供一种半导体集成电路器件的制造方法，其可以实时检测不合格的故障晶片。异常检测服务器存储从设备日志数据存储器中处理半导体晶片的半导体制造装置输出的装置对数据。此后，在多个终端信号接收机中，当接收到从半导体制造装置输出的批结束信号时，异常数据检测器在参考存储在第一检测条件存储器中的异常检测条件设置文件之后，基于所引用的内容，判断在装置日志数据存储器中存储的装置记录数据中是否存在异常数据。当检测到异常时，将检测结果输出到工程师PC和操作终端单元。

3. 发明授权

US06797442B2 Fabrication method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06797442B2
公开(公告)日：2004-09-28
申请号：US10614789
申请日：2003-07-09
申请人： Kazuyuki Tokorozuki , Tetsuji Yokouchi , Yoshiyuki Miyamoto , Koji Yamamoto
发明人： Kazuyuki Tokorozuki , Tetsuji Yokouchi , Yoshiyuki Miyamoto , Koji Yamamoto
IPC分类号： G03F900
CPC分类号： G03F7/70558
摘要： An average value of dimensions of resist patterns formed each time exposure processing is effected on semiconductor substrates of a predetermined number of lots, is compared with a target dimension. When a drift between each of the dimensions of the formed resist patterns and the target dimension is larger than a first value, exposure energy is corrected with a relatively large correction value &agr;1. When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the first value and larger than a second value, exposure energy is corrected with a relatively small correction value &agr;2. When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the second value, no exposure energy is corrected. Exposure processing is effected on a semiconductor substrate of the next lot by using the calculated exposure energy.
摘要翻译：将在预定批次的半导体衬底上进行每次曝光处理形成的抗蚀剂图案的尺寸的平均值与目标尺寸进行比较。当形成的抗蚀剂图案的每个尺寸和目标尺寸之间的漂移大于第一值时，以相对大的校正值α1校正曝光能量。当形成的抗蚀剂图案的每个尺寸与目标尺寸之间的漂移小于第一值并且大于第二值时，以相对较小的校正值α2校正曝光能量。当形成的抗蚀剂图案的每个尺寸和目标尺寸之间的漂移小于第二值时，不会校正曝光能量。通过使用计算出的曝光能量对下一批次的半导体衬底进行曝光处理。

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