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1. 发明授权

US4420696A Pulse train producing apparatus 失效
标题翻译：脉冲列车生产设备
公开(公告)号：US4420696A
公开(公告)日：1983-12-13
申请号：US238039
申请日：1981-02-25
申请人： Kazutoshi Gemma , Noriaki Hashimoto
发明人： Kazutoshi Gemma , Noriaki Hashimoto
IPC分类号： G06F1/10 , G06F1/06 , H03K5/15 , H03K19/21
CPC分类号： H03K5/1506 , G06F1/06
摘要： A pulse train producing apparatus is arranged such that a plurality of first pulse trains are produced correspondingly to a plurality of second pulse trains to be produced so that the leading or trailing edges of the pulses of each first train are adjusted in phase according to the intended phases of corresponding edges of the pulses of a corresponding one of the second pulse trains and the pulses of each first train overlap at their leading or trailing edge portions with the trailing or leading edge portions of a different one of the first trains and two of the first pulse trains having the overlapping portions are applied for cutting away the overlapping portions of the pulses of one of the two pulse trains.
摘要翻译：脉冲串制造装置被布置成使得相应于要产生的多个第二脉冲序列产生多个第一脉冲串，使得每个第一列的脉冲的前沿或后沿根据预期相位调整第二个脉冲序列的相应一个脉冲和每个第一列的脉冲的相应边缘的相位在它们的前缘或后缘部分重叠，其中第一列和第二列的不同之一的尾部或前沿部分施加具有重叠部分的第一脉冲串用于切除两个脉冲列之一的脉冲的重叠部分。

2. 发明授权

US4499536A Signal transfer timing control using stored data relating to operating speeds of memory and processor 失效
标题翻译：使用与存储器和处理器的操作速度相关的存储数据的信号传输定时控制
公开(公告)号：US4499536A
公开(公告)日：1985-02-12
申请号：US329048
申请日：1981-12-09
申请人： Kazutoshi Gemma , Michiyasu Ishibashi
发明人： Kazutoshi Gemma , Michiyasu Ishibashi
IPC分类号： G06F12/06 , G06F13/10 , G06F13/38 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4243 , G06F13/38
摘要： A memory controlling apparatus retains time information prepared based on performance of a memory and a processor, and determines timing of signal exchange between the memory and the processor based on the time information. An access time to the memory is reduced while maintaining a flexibility to a change of the access time due to increase of memory capacity or reconfiguration of the memory.
摘要翻译：存储器控制装置保持基于存储器和处理器的性能准备的时间信息，并且基于时间信息确定存储器和处理器之间的信号交换的定时。存储器的访问时间减少，同时由于存储器容量的增加或存储器的重新配置而保持对访问时间的改变的灵活性。

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