专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090085196A1 INTEGRATED CIRCUIT CHIP MANUFATURING METHOD AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：集成电路芯片制造方法和半导体器件
公开(公告)号：US20090085196A1
公开(公告)日：2009-04-02
申请号：US12328182
申请日：2008-12-04
申请人： Kazutaka Momoi , Nobuhiko Sato
发明人： Kazutaka Momoi , Nobuhiko Sato
IPC分类号： H01L23/12
CPC分类号： H01L21/76256 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , Y10S438/977
摘要： This invention moderates the difficulty in chip formation or packaging which accompanies thinning of a semiconductor region where an integrated circuit is formed. An integrated circuit chip manufacturing method includes a first bonding step of bonding a first support member to a first surface of a semiconductor substrate which has the first surface and a second surface and has a semiconductor region including an integrated circuit on a first surface side thereof, a thinning step of removing a second surface-side portion of the semiconductor substrate bonded to the first support member to leave the semiconductor region, thereby thinning the semiconductor substrate, a second bonding step of bonding a second support member to the second surface side of the thinned semiconductor substrate, and a chip forming step of forming chips by cutting the semiconductor region.
摘要翻译：本发明缓和了形成集成电路的半导体区域变薄的芯片形成或封装的难度。集成电路芯片的制造方法包括：将第一支撑构件接合到具有第一表面和第二表面的半导体衬底的第一表面并且在其第一表面侧上具有包括集成电路的半导体区域的第一接合步骤，去除接合到第一支撑构件的半导体衬底的第二表面侧部分以离开半导体区域，从而使半导体衬底变薄的薄化步骤，将第二支撑构件接合到第二表面侧的第二接合步骤薄化的半导体衬底，以及通过切割半导体区域形成芯片的芯片形成步骤。

2. 发明申请

US20060124961A1 Semiconductor substrate, manufacturing method thereof, and semiconductor device 审中-公开
标题翻译：半导体衬底，其制造方法和半导体器件
公开(公告)号：US20060124961A1
公开(公告)日：2006-06-15
申请号：US10540263
申请日：2004-12-14
申请人： Kiyofumi Sakaguchi , Kazuya Notsu , Kazutaka Momoi , Nobuhiko Sato
发明人： Kiyofumi Sakaguchi , Kazuya Notsu , Kazutaka Momoi , Nobuhiko Sato
IPC分类号： H01L31/0328
CPC分类号： H01L29/1054 , H01L21/76259 , H01L29/4933 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665
摘要： A separation layer is formed on a silicon substrate. An SiGe layer serving as a strain induction layer and a silicon layer serving as a strained semiconductor layer are formed sequentially on the separation layer to prepare a first substrate. The first substrate is bonded to a second substrate made of the same material as the silicon layer of the strained semiconductor layer. The structure is separated into two parts at the separation layer. When the residue of the separation layer and the SiGe layer are removed, and the surface is planarized by hydrogen annealing, an Si substrate having a strained silicon layer on the uppermost surface is obtained.
摘要翻译：在硅衬底上形成分离层。在分离层上依次形成用作应变感应层的SiGe层和用作应变半导体层的硅层，以制备第一衬底。第一衬底被结合到由与应变半导体层的硅层相同的材料制成的第二衬底上。该结构在分离层处分成两部分。当去除分离层和SiGe层的残余物并且通过氢退火使表面平坦化时，获得在最上表面上具有应变硅层的Si衬底。

3. 发明申请

US20050280119A1 Integrated circuit chip manufacturing method and semiconductor device 有权
标题翻译：集成电路芯片制造方法及半导体器件
公开(公告)号：US20050280119A1
公开(公告)日：2005-12-22
申请号：US11149145
申请日：2005-06-10
申请人： Kazutaka Momoi , Nobuhiko Sato
发明人： Kazutaka Momoi , Nobuhiko Sato
IPC分类号： H01L21/68 , H01L21/762 , H01L21/78 , H01L23/12
CPC分类号： H01L21/76256 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , Y10S438/977
摘要： This invention moderates the difficulty in chip formation or packaging which accompanies thinning of a semiconductor region where an integrated circuit is formed. An integrated circuit chip manufacturing method includes a first bonding step of bonding a first support member to a first surface of a semiconductor substrate which has the first surface and a second surface and has a semiconductor region including an integrated circuit on a first surface side thereof, a thinning step of removing a second surface-side portion of the semiconductor substrate bonded to the first support member to leave the semiconductor region, thereby thinning the semiconductor substrate, a second bonding step of bonding a second support member to the second surface side of the thinned semiconductor substrate, and a chip forming step of forming chips by cutting the semiconductor region.
摘要翻译：本发明缓和了形成集成电路的半导体区域变薄的芯片形成或封装的难度。集成电路芯片的制造方法包括：将第一支撑构件接合到具有第一表面和第二表面的半导体衬底的第一表面并且在其第一表面侧上具有包括集成电路的半导体区域的第一接合步骤，去除接合到第一支撑构件的半导体衬底的第二表面侧部分以离开半导体区域，从而使半导体衬底变薄的薄化步骤，将第二支撑构件接合到第二表面侧的第二接合步骤薄化的半导体衬底，以及通过切割半导体区域形成芯片的芯片形成步骤。

4. 发明申请

US20060049487A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060049487A1
公开(公告)日：2006-03-09
申请号：US11222895
申请日：2005-09-08
申请人： Nobuhiko Sato , Shigeru Kido , Kazutaka Momoi
发明人： Nobuhiko Sato , Shigeru Kido , Kazutaka Momoi
IPC分类号： H01L21/78
CPC分类号： H01L21/02203 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/02307 , H01L21/02337 , H01L21/31675 , H01L21/78 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method is disclosed. A semiconductor substrate having a separation region and a semiconductor region which covers the separation region entirely is prepared. One or a plurality of circuit elements are formed in the semiconductor region. The semiconductor substrate is split at the separation region.
摘要翻译：公开了半导体器件制造方法。制备具有分离区域和完全覆盖分离区域的半导体区域的半导体衬底。在半导体区域中形成有一个或多个电路元件。半导体衬底在分离区域处分裂。

5. 发明授权

US06639327B2 Semiconductor member, semiconductor device and manufacturing methods thereof 失效
公开(公告)号：US06639327B2
公开(公告)日：2003-10-28
申请号：US09899257
申请日：2001-07-06
申请人： Kazutaka Momoi , Takao Yonehara , Nobuhiko Sato , Masataka Ito , Noriaki Honma
发明人： Kazutaka Momoi , Takao Yonehara , Nobuhiko Sato , Masataka Ito , Noriaki Honma
IPC分类号： H01L2358
CPC分类号： H01L21/76251 , H01L21/3226 , H01L21/764
摘要： In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member is manufactured by interposing the microgaps between two substrates.

6. 发明授权

US07696065B2 Method of manufacturing a semiconductor device by forming separation regions which do not extend to the peripherals of a substrate, and structures thereof 失效
标题翻译：通过形成不延伸到基板的外围的分离区域制造半导体器件的方法及其结构
公开(公告)号：US07696065B2
公开(公告)日：2010-04-13
申请号：US11222895
申请日：2005-09-08
申请人： Nobuhiko Sato , Shigeru Kido , Kazutaka Momoi
发明人： Nobuhiko Sato , Shigeru Kido , Kazutaka Momoi
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/02203 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/02307 , H01L21/02337 , H01L21/31675 , H01L21/78 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method is disclosed. A semiconductor substrate having a separation region and a semiconductor region which covers the separation region entirely is prepared. One or a plurality of circuit elements are formed in the semiconductor region. The semiconductor substrate is split at the separation region.
摘要翻译：公开了半导体器件制造方法。制备具有分离区域和完全覆盖分离区域的半导体区域的半导体衬底。在半导体区域中形成有一个或多个电路元件。半导体衬底在分离区域处分裂。

7. 发明授权

US07473617B2 Integrated circuit chip manufacturing method and semiconductor device 有权
标题翻译：集成电路芯片制造方法及半导体器件
公开(公告)号：US07473617B2
公开(公告)日：2009-01-06
申请号：US11149145
申请日：2005-06-10
申请人： Kazutaka Momoi , Nobuhiko Sato
发明人： Kazutaka Momoi , Nobuhiko Sato
IPC分类号： H01L21/30
CPC分类号： H01L21/76256 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , Y10S438/977
摘要： This invention moderates the difficulty in chip formation or packaging which accompanies thinning of a semiconductor region where an integrated circuit is formed. An integrated circuit chip manufacturing method includes a first bonding step of bonding a first support member to a first surface of a semiconductor substrate which has the first surface and a second surface and has a semiconductor region including an integrated circuit on a first surface side thereof, a thinning step of removing a second surface-side portion of the semiconductor substrate bonded to the first support member to leave the semiconductor region, thereby thinning the semiconductor substrate, a second bonding step of bonding a second support member to the second surface side of the thinned semiconductor substrate, and a chip forming step of forming chips by cutting the semiconductor region.
摘要翻译：本发明缓和了形成集成电路的半导体区域变薄的芯片形成或封装的难度。集成电路芯片的制造方法包括：将第一支撑构件接合到具有第一表面和第二表面的半导体衬底的第一表面并且在其第一表面侧上具有包括集成电路的半导体区域的第一接合步骤，去除接合到第一支撑构件的半导体衬底的第二表面侧部分以离开半导体区域，从而使半导体衬底变薄的薄化步骤，将第二支撑构件接合到第二表面侧的第二接合步骤薄化的半导体衬底，以及通过切割半导体区域形成芯片的芯片形成步骤。

8. 发明申请

US20060070884A1 Electrochemical processing apparatus and method 审中-公开
标题翻译：电化学处理装置及方法
公开(公告)号：US20060070884A1
公开(公告)日：2006-04-06
申请号：US11245912
申请日：2005-10-06
申请人： Kazutaka Momoi , Kazutaka Yanaqita , Nobuhiko Sato
发明人： Kazutaka Momoi , Kazutaka Yanaqita , Nobuhiko Sato
IPC分类号： C25D5/02
CPC分类号： C25D17/10 , C25D5/02 , C25D11/005 , C25D11/02
摘要： A processing apparatus electrochemically processes part of a first surface of a member having the first surface and a second surface. The processing apparatus includes a support which supports the member to expose the first surface, a first electrode which is arranged to oppose a first portion of the first surface, a second electrode which is arranged to oppose a second portion of the first surface, a third electrode which applies a potential to the member from a second surface side, and a processing bath to fill a space defined by the first and second electrodes and the member with a processing liquid.
摘要翻译：一种处理装置，电化学处理具有第一表面和第二表面的构件的第一表面的一部分。处理装置包括支撑构件以露出第一表面的支撑件，布置成与第一表面的第一部分相对的第一电极，布置成与第一表面的第二部分相对的第二电极，第三电极电极，其从第二表面侧向构件施加电位;以及处理槽，用处理液填充由第一和第二电极和构件限定的空间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式