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1. 发明授权

US07190211B2 Semiconductor device equipped with a voltage step-up circuit 有权
标题翻译：配有升压电路的半导体装置
公开(公告)号：US07190211B2
公开(公告)日：2007-03-13
申请号：US11059255
申请日：2005-02-15
申请人： Michio Nakagawa , Kazuo Sato , Hiromi Uenoyama , Yasuyuki Ohnishi , Kazunori Torii
发明人： Michio Nakagawa , Kazuo Sato , Hiromi Uenoyama , Yasuyuki Ohnishi , Kazunori Torii
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C5/145 , G05F1/468 , H01L27/0222 , H01L29/94
摘要： A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.
摘要翻译：半导体器件配备有具有一系列多个电荷泵单元的升压电路。每个单元具有良好的分离型MOS晶体管。晶体管的分离阱耦合到高电位，以在N型阱和P型衬底之间以及在N型阱和P型阱之间形成双重反向偏压。这允许MOS晶体管的阈值Vth保持在低电平。这些单元设置有时钟，其电流供应能力被限制到预定条件（通过启动信号启动升压电路之后经过了预定时间段或者输出电压已经达到预定水平）。时钟的这种限制有助于抑制起动期间升压电路的功耗，从而减小电源电压的幅度变化。

2. 发明申请

US20070122964A1 Semiconductor Device Equipped with a Voltage Step-Up Circuit 审中-公开
标题翻译：配有升压电路的半导体器件
公开(公告)号：US20070122964A1
公开(公告)日：2007-05-31
申请号：US11669051
申请日：2007-01-30
申请人： Michio NAKAGAWA , Kazuo SATO , Hiromi UENOYAMA , Yasuyuki OHNISHI , Kazunori TORII
发明人： Michio NAKAGAWA , Kazuo SATO , Hiromi UENOYAMA , Yasuyuki OHNISHI , Kazunori TORII
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： G11C5/145 , G05F1/468 , H01L27/0222 , H01L29/94
摘要： A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.
摘要翻译：半导体器件配备有具有一系列多个电荷泵单元的升压电路。每个单元具有良好的分离型MOS晶体管。晶体管的分离阱耦合到高电位，以在N型阱和P型衬底之间以及在N型阱和P型阱之间形成双重反向偏压。这允许MOS晶体管的阈值Vth保持在低电平。这些单元设置有时钟，其电流供应能力被限制到预定条件（通过启动信号启动升压电路之后经过了预定时间段或者输出电压已经达到预定水平）。时钟的这种限制有助于抑制起动期间升压电路的功耗，从而减小电源电压的幅度变化。

3. 发明申请

US20050134362A1 Semiconductor device equipped with a voltage step-up circuit 有权
标题翻译：配有升压电路的半导体装置
公开(公告)号：US20050134362A1
公开(公告)日：2005-06-23
申请号：US11059255
申请日：2005-02-15
申请人： Michio Nakagawa , Kazuo Sato , Hiromi Uenoyama , Yasuyuki Ohnishi , Kazunori Torii
发明人： Michio Nakagawa , Kazuo Sato , Hiromi Uenoyama , Yasuyuki Ohnishi , Kazunori Torii
IPC分类号： G05F1/46 , G05F1/10
CPC分类号： G11C5/145 , G05F1/468 , H01L27/0222 , H01L29/94
摘要： A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.
摘要翻译：半导体器件配备有具有一系列多个电荷泵单元的升压电路。每个单元具有良好的分离型MOS晶体管。晶体管的分离阱耦合到高电位，以在N型阱和P型衬底之间以及在N型阱和P型阱之间形成双重反向偏压。这允许MOS晶体管的阈值Vth保持在低电平。这些单元设置有时钟，其电流供应能力被限制到预定条件（通过启动信号启动升压电路之后经过了预定时间段或者输出电压已经达到预定水平）。时钟的这种限制有助于抑制起动期间升压电路的功耗，从而减小电源电压的幅度变化。

4. 发明授权

US06888399B2 Semiconductor device equipped with a voltage step-up circuit 失效
公开(公告)号：US06888399B2
公开(公告)日：2005-05-03
申请号：US10358491
申请日：2003-02-04
申请人： Michio Nakagawa , Kazuo Sato , Hiromi Uenoyama , Yasuyuki Ohnishi , Kazunori Torii
发明人： Michio Nakagawa , Kazuo Sato , Hiromi Uenoyama , Yasuyuki Ohnishi , Kazunori Torii
IPC分类号： G05F1/46 , G05F1/10 , G05F3/02
CPC分类号： G11C5/145 , G05F1/468 , H01L27/0222 , H01L29/94
摘要： A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

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