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1. 发明授权

US07036060B2 Semiconductor integrated circuit and its analyzing method 失效
公开(公告)号：US07036060B2
公开(公告)日：2006-04-25
申请号：US10452195
申请日：2003-06-03
申请人： Michinobu Nakao , Ryo Yamagata , Kazumi Hatayama , Seiji Kobayashi , Kazunori Hikone , Kotaro Shimamura
发明人： Michinobu Nakao , Ryo Yamagata , Kazumi Hatayama , Seiji Kobayashi , Kazunori Hikone , Kotaro Shimamura
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.

2. 发明授权

US06640198B2 Semiconductor device having self test function 失效
标题翻译：具有自检功能的半导体器件
公开(公告)号：US06640198B2
公开(公告)日：2003-10-28
申请号：US09941754
申请日：2001-08-30
申请人： Masahide Miyazaki , Kazumi Hatayama , Kazunori Hikone , Seiji Kobayashi
发明人： Masahide Miyazaki , Kazumi Hatayama , Kazunori Hikone , Seiji Kobayashi
IPC分类号： G06F1125
CPC分类号： G11C29/16
摘要： The present invention relates to an LSI which performs a self test using its built-in test function according to a test program stored in an on-chip memory. An object of the present invention is to efficiently perform the self test in the case where branching to an address out of the address space of the on-chip memory occurs. A program counter 101 stores addresses of a memory 117 and an external memory. A test program counter 108 stores an address of the memory 117. In a test mode, a program counter switching section 109 performs control so that when an address of the memory 117 is detected in the program counter 101, the address value of the program counter 101 is selected, whereas when an address of the external memory is detected in the program counter 101, the address value of the test program counter 108 is selected. A signature compression circuit 110 signature-compresses and holds the output value of the program counter 101.
摘要翻译：本发明涉及根据存储在片上存储器中的测试程序使用其内置测试功能进行自检的LSI。本发明的目的是在分支到片上存储器的地址空间中的地址发生的情况下有效地执行自检。程序计数器101存储存储器117和外部存储器的地址。测试程序计数器108存储存储器117的地址。在测试模式中，程序计数器切换部109执行控制，使得当在程序计数器101中检测到存储器117的地址时，程序计数器的地址值 101，而当在程序计数器101中检测到外部存储器的地址时，选择测试程序计数器108的地址值。签名压缩电路110签名压缩并保持程序计数器101的输出值。

3. 发明授权

US06317853B1 Apparatus for making test data and method thereof 失效
标题翻译：用于制作测试数据的装置及其方法
公开(公告)号：US06317853B1
公开(公告)日：2001-11-13
申请号：US08847592
申请日：1997-04-24
申请人： Kazunori Hikone , Kazumi Hatayama , Takao Nishida , Hiromichi Yamada
发明人： Kazunori Hikone , Kazumi Hatayama , Takao Nishida , Hiromichi Yamada
IPC分类号： G01R3128
CPC分类号： G06F11/263
摘要： An apparatus for providing test data used for detection of defects which occur in manufacturing functional blocks of a processor LSI is provided with a test pattern producing part for detecting a fault of the functional block at a block edge of the functional block, based on logic data of the functional block, with regard to one operation of the processor LSI which operates the functional block for the test data to be produced, the test pattern at the block edge of the functional block being such as to satisfy the conditions of an input signal to the block edge of the functional block when an instruction on the one operation is executed, and the conditions of an output signal from the block edge of the functional block being observable from the outside of the processor LSI when the instruction is executed. The apparatus also has an instruction sequence producing part for producing an instruction sequence in a machine language for the processor LSI by which an output from the block edge of the functional block becomes detectable at an external terminal of the processor LSI.
摘要翻译：一种用于提供用于检测在处理器LSI的制造功能块中发生的缺陷的测试数据的装置，设置有用于根据逻辑数据检测在功能块的块边缘处的功能块的故障的测试模式产生部分功能块的功能块的功能块的操作的一个操作对于要产生的测试数据的功能块的一个操作，功能块的块边缘处的测试图案要满足输入信号的条件当执行一个操作的指令时，功能块的块边缘，以及当执行指令时来自处理器LSI的外部的可从功能块的块边缘输出的输出信号的条件。该装置还具有指令序列生成部分，用于产生用于处理器LSI的机器语言的指令序列，通过该指令序列，功能块的块边沿的输出在处理器LSI的外部端可以检测到。

4. 发明授权

US5329532A Logic circuit with additional circuit for carrying out delay test 失效
标题翻译：具有进行延迟测试的附加电路的逻辑电路
公开(公告)号：US5329532A
公开(公告)日：1994-07-12
申请号：US755837
申请日：1991-09-06
申请人： Mitsuji Ikeda , Kazumi Hatayama , Terumine Hayashi
发明人： Mitsuji Ikeda , Kazumi Hatayama , Terumine Hayashi
IPC分类号： G01R31/28 , G01R31/3185 , H04B17/00
CPC分类号： G01R31/318541 , G01R31/31858
摘要： The first and second flip-flop circuits are connected in series included within a combinational logic for carrying out a delay test. The first and second flip-flop circuits are provided with control pins, system clock pins, scan clock pins, system data pins and scan data pins, respectively. A delay time propagated from the first flip-flop circuit to the second flip-flop circuit through the path of the combinational logic to be tested is measured by detecting an input time to the first flip-flop circuit by the system clock signal to the first flip-flop circuit in response to an input signal to the control pins and a time stored in the second flip-flop circuit corresponding to output system data from the first flip-flop circuit. By measuring the delay time, whether the combinational logic is normal or abnormal is detected.
摘要翻译：第一和第二触发器电路串联连接在用于进行延迟测试的组合逻辑中。第一和第二触发器电路分别具有控制引脚，系统时钟引脚，扫描时钟引脚，系统数据引脚和扫描数据引脚。通过检测到第一触发器电路的输入时间，通过系统时钟信号检测到第一触发器电路的第一触发器电路到第一触发器电路的第一触发器电路触发器电路响应于对控制引脚的输入信号以及与第一触发器电路的输出系统数据相对应的存储在第二触发器电路中的时间。通过测量延迟时间，检测组合逻辑是正常还是异常。

5. 发明授权

US06484294B1 Semiconductor integrated circuit and method of designing the same 失效
标题翻译：半导体集成电路及其设计方法
公开(公告)号：US06484294B1
公开(公告)日：2002-11-19
申请号：US09462913
申请日：2000-01-18
申请人： Yoshikazu Kiyoshige , Michinobu Nakao , Kazumi Hatayama , Takashi Hotta
发明人： Yoshikazu Kiyoshige , Michinobu Nakao , Kazumi Hatayama , Takashi Hotta
IPC分类号： G06F1750
CPC分类号： G01R31/318583 , G01R31/3016
摘要： A method for designing a semiconductor integrated circuit while minimizing any increase in the area of its logic circuit under test. Circuit data about the semiconductor integrated circuit are received, and transition signal occurrence probabilities of all scanning function-equipped storage elements involved are computed by use of the circuit data. In keeping with the transition signal occurrence probabilities thus computed and based on predetermined parameters, the method permits selection of scanning function-equipped storage elements that may be replaced by delay test-ready scanning function-equipped storage elements.
摘要翻译：一种用于设计半导体集成电路同时最小化其被测逻辑电路的面积的任何增加的方法。接收关于半导体集成电路的电路数据，并且通过使用电路数据来计算所涉及的所有配备有扫描功能的存储元件的转换信号发生概率。为了与由此计算出的过渡信号发生概率和基于预定参数保持一致，该方法允许选择可由具有延迟测试就绪扫描功能的存储元件代替的具有扫描功能的存储元件。

6. 发明授权

US6038691A Method of analyzing logic circuit test points, apparatus for analyzing logic circuit test points and semiconductor integrated circuit with test points 失效
标题翻译：分析逻辑电路测试点的方法，用于分析逻辑电路测试点的设备和具有测试点的半导体集成电路
公开(公告)号：US6038691A
公开(公告)日：2000-03-14
申请号：US3500
申请日：1998-01-06
申请人： Michinobu Nakao , Kazumi Hatayama , Jun Hirano
发明人： Michinobu Nakao , Kazumi Hatayama , Jun Hirano
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318583
摘要： A test point analyzing apparatus determines a distinction between capability and incapability of insertion of a test point and a circuit modifying way when a test point is capable of being inserted for each of the test point types to each of the signal lines in a semiconductor integrated circuit by using circuit information, a test point insertion library, and test point insertion. Then, test point indexes to test point candidates capable of being inserted are calculated, and test point candidates having a large testability are selected based on the indexes, and the selected test point candidates are registered in test point information. Such processing is repeated until a predetermined condition of completing the test point analysis process is realized. In the apparatus, a test point index calculation portion calculates test point index information including CRF (Cost Reduction Factor) of each signal line from circuit information, determines a predetermined number of test point candidates in order of the CRF, and calculates COP (Controllability Observability Procedure, hereinafter referred to as test cost) when each of the test point candidates is assumed to be inserted. By setting candidates of the minimum COP as test points, a test point determining portion searches the other test point candidates not intersecting with an effect region of the test points in increasing order, and if there exists a test point candidate not intersecting with an effect region, the test point is added to a new test point group.
摘要翻译：当测试点能够针对每个测试点类型插入到半导体集成电路中的每个信号线时，测试点分析装置确定测试点的插入能力和不适应性之间的区别以及电路修改方式通过使用电路信息，测试点插入库和测试点插入。然后，对能够插入的测试点候选的测试点索引进行计算，并且基于索引来选择具有较大可测试性的测试点候选，并且将所选择的测试点候选登记在测试点信息中。重复这种处理，直到实现完成测试点分析处理的预定条件。在该装置中，测试点索引计算部分根据电路信息计算包括每个信号线的CRF（Cost Reduction Factor）的测试点索引信息，按照CRF的顺序确定预定数量的测试点候选，并且计算COP（可控性可观察性当假设每个测试点候选被插入时，程序，以下称为测试成本）。通过将最小COP的候选项设置为测试点，测试点确定部分按照增加的顺序搜索与测试点的效果区域不相交的其他测试点候选，并且如果存在不与效果区域相交的测试点候选，将测试点添加到新的测试点组。

7. 发明授权

US6032280A Apparatus for making test data and method thereof 失效
公开(公告)号：US6032280A
公开(公告)日：2000-02-29
申请号：US847592
申请日：1997-04-24
申请人： Kazunori Hikone , Kazumi Hatayama , Takao Nishida , Hiromichi Yamada
发明人： Kazunori Hikone , Kazumi Hatayama , Takao Nishida , Hiromichi Yamada
摘要： An apparatus for producing test data used for detection of defects which occur in manufacturing functional blocks of a processor LSI is provided with a test pattern producing part for detecting a fault of the functional block at a block edge of the functional block, based on logic data of the functional block, with regard to one operation of the processor LSI which operates the functional block for the test data to be produced, the test pattern at the block edge of the functional block being such as to satisfy the conditions of an input signal to the block edge of the functional block when an instruction on the one operation is executed, and the conditions of an output signal from the block edge of the functional block being observable from the outside of the processor LSI when the instruction is executed. The apparatus also has an instruction sequence producing part for producing an instruction sequence in a machine language for the processor LSI by which an output from the block edge of the functional block becomes detectable at an external terminal of the processor LSI.

8. 发明授权

US4956818A Memory incorporating logic LSI and method for testing the same LSI 失效
标题翻译：内置逻辑LSI和测试相同LSI的方法
公开(公告)号：US4956818A
公开(公告)日：1990-09-11
申请号：US251913
申请日：1988-09-30
申请人： Kazumi Hatayama , Terumine Hayashi
发明人： Kazumi Hatayama , Terumine Hayashi
IPC分类号： H01L21/66 , G01R31/28 , G01R31/317 , G01R31/3185 , G06F11/22 , G11C29/00 , G11C29/12 , G11C29/56
CPC分类号： G11C29/12 , G06F11/2273
摘要： A memory incorporating logic Large Scale Integration (LSI) and a method for testing the same LSI includes signal path switching circuit portions which are disposed in the paths of a memory portion and a logic circuit portion. A test signal input and an output signal can be observed at an input and output terminal portion so as to be able to effect a dynamic function test of the memory portion. Further there is disposed a logic circuit test signal memory circuit portion, which switches over the signal path switching circuit portions to the logic circuit portion so as to be able to effect a test of the logic circuit portion, independently of the state of the memory portion.

9. 发明授权

US4710930A Method and apparatus for diagnosing a LSI chip 失效
标题翻译：用于诊断LSI芯片的方法和装置
公开(公告)号：US4710930A
公开(公告)日：1987-12-01
申请号：US825600
申请日：1986-02-03
申请人： Kazumi Hatayama , Terumine Hayashi
发明人： Kazumi Hatayama , Terumine Hayashi
IPC分类号： G06F11/22 , G01R31/28 , G01R31/3185 , G11C29/32
CPC分类号： G01R31/318566 , G01R31/318558 , G11C29/32
摘要： Disclosed is a method of level sensitive testing of a logic array system and an LSI chip having testing means incorporated therein. The present invention is especially suitable for testing a RAM and the function of a logic unit which is a functional peripheral of the RAM. The LSI chip comprises means for selecting a specific address of the RAM, means for writing a signal at the specific address of the RAM and reading out the data from the specific address of the RAM, and means for selecting the operation of the chip between a usual operation mode and a scan-in/scan-out diagnostic mode for testing the RAM or functional peripheral of the RAM. Testing can be easily conducted by addition of a small number of logic elements. The larger the number of address signal lines and the number of data signal lines of the RAM, the more effective the testing method becomes.
摘要翻译：公开了一种逻辑阵列系统的电平敏感测试方法和其中结合有测试装置的LSI芯片。本发明特别适合于测试RAM和作为RAM的功能外设的逻辑单元的功能。 LSI芯片包括用于选择RAM的特定地址的装置，用于在RAM的特定地址处写入信号并从RAM的特定地址读出数据的装置，以及用于选择芯片的操作的装置，通常的操作模式和用于测试RAM的RAM或功能外围设备的扫描/扫描输出诊断模式。可以通过添加少量的逻辑元件轻松实现测试。地址信号线数量和RAM数据信号线数量越多，测试方法变得越有效。

10. 发明授权

US4613970A Integrated circuit device and method of diagnosing the same 失效
标题翻译：集成电路装置及其诊断方法
公开(公告)号：US4613970A
公开(公告)日：1986-09-23
申请号：US575706
申请日：1984-01-31
申请人： Ikuro Masuda , Hideo Maejima , Terumine Hayashi , Kazumi Hatayama
发明人： Ikuro Masuda , Hideo Maejima , Terumine Hayashi , Kazumi Hatayama
IPC分类号： G01R31/28 , G01R31/3185 , G01R15/12
CPC分类号： G01R31/318558 , G01R31/318516
摘要： A method of diagnosing an integrated circuit device having a plurality of combinational circuits, at least one input memory circuit connected to an input side of the combinational circuits, and an output memory circuit connected to an output side of the combinational circuits is disclosed. An input diagnostic signal is selectively applied to at least one input memory circuit connected to a given one of the combinational circuits, to read out a diagnostic signal stored in an output memory circuit connected to the given combinational circuit. Further, an integrated circuit device is disclosed which is suited to be diagnosed in the above method.
摘要翻译：一种用于诊断具有多个组合电路的集成电路器件的方法，连接到组合电路的输入侧的至少一个输入存储器电路以及连接到组合电路的输出侧的输出存储器电路。输入诊断信号被选择性地施加到连接到组合电路中给定的一个的至少一个输入存储器电路，以读出存储在连接到给定组合电路的输出存储器电路中的诊断信号。此外，公开了适用于以上述方法进行诊断的集成电路装置。

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