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1. 发明授权

US5590290A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement 失效
标题翻译：用于控制总线进行传送周期而不插入确认周期的方法
公开(公告)号：US5590290A
公开(公告)日：1996-12-31
申请号：US487401
申请日：1995-06-07
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42 , G06F3/04
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.
摘要翻译：一种信息处理系统，其中作为执行对模块的读取访问以作为从机操作的主机的模块请求总线仲裁器以提供具有总线主控请求信号的母线的掌握，并且它同时断言最后一个周期信号，以通知总线仲裁器下一个周期将是主机使用的最后一个周期的事实。随后，当主机已经使用由总线仲裁器通过总线使用授权信号授予的总线时，它通过在下一个周期中使用总线将地址传送到从机，从而开始读取访问。读取权限后，主人释放总线主控权。只有当从站未能接受传送的地址时，它会在地址的传输周期不被接受的两个周期之后重新生成重试请求信号。在这种情况下，在断言信号的周期之前执行传送两个周期的模块再次执行之前执行的传送。因此，要传输的地址只能在一个周期内传输到模块准备好接受地址。

2. 发明授权

US5428753A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment 失效
公开(公告)号：US5428753A
公开(公告)日：1995-06-27
申请号：US60055
申请日：1993-05-13
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42 , G06F13/40
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

3. 发明授权

US5657458A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment 失效
标题翻译：用于控制总线进行传送周期而不插入确认周期的方法
公开(公告)号：US5657458A
公开(公告)日：1997-08-12
申请号：US480397
申请日：1995-06-07
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.
摘要翻译：一种信息处理系统，其中作为执行对模块的读取访问以作为从机操作的主机的模块请求总线仲裁器以提供具有总线主控请求信号的总线主控性，并且同时断言最后一个周期信号，以通知总线仲裁器下一个周期将是主机使用的最后一个周期的事实。随后，当主机已经使用由总线仲裁器通过总线使用授权信号授予的总线时，它通过在下一个周期中使用总线将地址传送到从机，从而开始读取访问。读取权限后，主人释放总线主控权。只有当从站未能接受传送的地址时，它会在地址的传输周期不被接受的两个周期之后重新生成重试请求信号。在这种情况下，在断言信号的周期之前执行传送两个周期的模块再次执行之前执行的传送。因此，要传输的地址只能在一个周期内传输到模块准备好接受地址。

4. 发明授权

US5604874A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment 失效
公开(公告)号：US5604874A
公开(公告)日：1997-02-18
申请号：US480395
申请日：1995-06-07
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42 , G06F15/16
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

5. 发明授权

US06219735B1 Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement 失效
标题翻译：用于控制总线进行传送周期而不插入确认周期的方法
公开(公告)号：US06219735B1
公开(公告)日：2001-04-17
申请号：US09477666
申请日：2000-01-05
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F1312
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.
摘要翻译：一种信息处理系统，其中作为执行对模块的读取访问以作为从机操作的主机的模块请求总线仲裁器以提供具有总线主控请求信号的母线的掌握，并且它同时断言最后一个周期信号，以通知总线仲裁器下一个周期将是主机使用的最后一个周期的事实。随后，当主机已经使用由总线仲裁器通过总线使用授权信号授予的总线时，它通过在下一个周期中使用总线将地址传送到从机，从而开始读取访问。读取权限后，主人释放总线主控权。只有当从站未能接受传送的地址时，它会在地址的传输周期不被接受的两个周期之后重新生成重试请求信号。在这种情况下，在断言信号的周期之前执行传送两个周期的模块再次执行之前执行的传送。因此，要传输的地址只能在一个周期内传输到模块准备好接受地址。

6. 发明授权

US6047345A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment 失效
公开(公告)号：US6047345A
公开(公告)日：2000-04-04
申请号：US78713
申请日：1998-05-14
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

7. 发明授权

US5774679A Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement 失效
公开(公告)号：US5774679A
公开(公告)日：1998-06-30
申请号：US774614
申请日：1996-12-30
申请人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
发明人： Nobukazu Kondo , Seiji Kaneko , Hideaki Gemma , Tetsuhiko Okada , Kazuhiko Komori , Koichi Okazawa
IPC分类号： G06F13/362 , G06F13/00 , G06F13/12 , G06F13/364 , G06F13/38 , G06F13/42 , G06F13/14
CPC分类号： G06F13/364
摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

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