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1. 发明授权

US5631866A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5631866A
公开(公告)日：1997-05-20
申请号：US444579
申请日：1995-05-19
申请人： Tomoharu Oka , Yukinori Kodama , Katsumi Shigenobu
发明人： Tomoharu Oka , Yukinori Kodama , Katsumi Shigenobu
IPC分类号： G11C11/409 , G11C7/10 , G11C11/407 , G11C11/413 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1072
摘要： A synchronous DRAM is disclosed. The DRAM comprises an input buffer, a memory cell array, an output buffer, a signal transfer circuit, first and second latch circuits, and a controller. The input buffer receives an operation control signal supplied externally. The memory cell array has a plurality of memory cells for storing data. The output buffer outputs a data signal read from the memory cells. The signal transfer circuit reads a data signal from one of the memory cells in accordance with the operation control signal from the input buffer, and sends this read data signal to the output buffer. The first and second latch circuits, provided between the input buffer and the output buffer, latch the associated input signals in response to a clock signal. The controller controls the latching operation of the second latch circuit by delaying the clock signal input to the second latch circuit for a period of time from when the first latch circuit receives input from the input buffer to when the read data signal arrives at the second latch circuit.
摘要翻译：公开了一种同步DRAM。 DRAM包括输入缓冲器，存储单元阵列，输出缓冲器，信号传输电路，第一和第二锁存电路以及控制器。输入缓冲器接收外部提供的操作控制信号。存储单元阵列具有用于存储数据的多个存储单元。输出缓冲器输出从存储器单元读取的数据信号。信号传送电路根据来自输入缓冲器的操作控制信号从一个存储单元读取数据信号，并将该读取的数据信号发送到输出缓冲器。设置在输入缓冲器和输出缓冲器之间的第一和第二锁存电路响应于时钟信号锁存相关联的输入信号。控制器通过将输入到第二锁存电路的时钟信号延迟一段时间，从第一锁存电路从输入缓冲器接收到从读取数据信号到达第二锁存器的时间段来控制第二锁存电路的锁存操作电路。

2. 发明授权

US5483497A Semiconductor memory having a plurality of banks usable in a plurality of bank configurations 失效
标题翻译：半导体存储器，具有可在多个存储体配置中使用的多个存储体
公开(公告)号：US5483497A
公开(公告)日：1996-01-09
申请号：US277486
申请日：1994-07-19
申请人： Hirohiko Mochizuki , Yoshihiro Takemae , Yukinori Kodama , Makoto Yanagisawa , Katsumi Shigenobu
发明人： Hirohiko Mochizuki , Yoshihiro Takemae , Yukinori Kodama , Makoto Yanagisawa , Katsumi Shigenobu
IPC分类号： G11C11/41 , G06F12/06 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C7/00
CPC分类号： G06F12/0623 , G11C8/12
摘要： A semiconductor memory having a plurality of banks, a first specify unit, and a second specify unit. The first specify unit is used to specify one of the banks by decoding a bank address signal contained in a row address signal. The second specify unit is used to specify one of the banks by decoding the bank address signal contained in the row address signal, according to bank status signals that indicate whether or not each of the banks is activated. Therefore, the semiconductor memory is used for different bank configurations. Namely, with this arrangement, the semiconductor memory is capable of serving as a memory having a smaller number of banks, to thereby improve convenience.
摘要翻译：具有多个存储体的半导体存储器，第一指定单元和第二指定单元。第一指定单元用于通过解码包含在行地址信号中的存储体地址信号来指定存储体之一。第二指定单元用于根据指示每个存储体是否被激活的存储体状态信号对包含在行地址信号中的存储体地址信号进行解码来指定存储区之一。因此，半导体存储器用于不同的存储体配置。也就是说，通过这种布置，半导体存储器能够用作具有较少数量的存储体的存储器，从而提高方便性。

3. 发明授权

US07171592B2 Self-testing circuit in semiconductor memory device 有权
标题翻译：半导体存储器件中的自检电路
公开(公告)号：US07171592B2
公开(公告)日：2007-01-30
申请号：US10360862
申请日：2003-02-10
申请人： Kenji Togashi , Morihiko Hamada , Shigekazu Aoki , Katsumi Shigenobu , Yukio Saka , Yoshikazu Arisaka , Toyoji Sawada , Tadashi Asai
发明人： Kenji Togashi , Morihiko Hamada , Shigekazu Aoki , Katsumi Shigenobu , Yukio Saka , Yoshikazu Arisaka , Toyoji Sawada , Tadashi Asai
IPC分类号： G06F11/00
CPC分类号： G11C29/4401 , G11C29/789 , G11C29/848
摘要： A semiconductor memory device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit includes a comparison circuit which compares write data with read data with respect to normal memory blocks and redundant memory blocks, and a decision circuit which decides if the semiconductor memory device is good or defective based on the plurality of comparison result signals. A signal transfer and holding circuit is connected between the comparison circuit and the decision circuit to transfer the plurality of comparison result signals to the decision circuit and to supply the plurality of comparison result signals to the self-redundancy circuit as a test result.
摘要翻译：半导体存储器件包括具有简单结构的自检电路和自冗余电路。自检电路包括比较电路，其将写入数据与读取数据相对于正常存储器块和冗余存储器块进行比较，以及判定电路，其基于多个比较结果信号来判定半导体存储器件是否良好或有缺陷。信号传送和保持电路连接在比较电路和判定电路之间，以将多个比较结果信号传送到判定电路，并将多个比较结果信号提供给自冗余电路作为测试结果。

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