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1. 发明授权

US5684975A Method for use in translating virtual addresses into absolute addresses 失效
标题翻译：用于将虚拟地址转换为绝对地址的方法
公开(公告)号：US5684975A
公开(公告)日：1997-11-04
申请号：US453140
申请日：1995-05-30
申请人： Karl Jean Duvalsaint , Mark Steven Farrell , Barry Watson Krumm , Donald William McCauley , Charles Franklin Webb
发明人： Karl Jean Duvalsaint , Mark Steven Farrell , Barry Watson Krumm , Donald William McCauley , Charles Franklin Webb
IPC分类号： G06F12/10 , G06F12/00 , G06F9/26 , G06F9/34 , G06F12/02
CPC分类号： G06F12/109 , G06F12/10
摘要： In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.
摘要翻译：在处理系统中，在虚拟地址和绝对地址之间便于翻译。该系统包括多个寄存器和用第一组地址转换参数加载它们的机制。加法器将平移原点寄存器与偏移寄存器相加以产生基准加偏移值。逻辑电路选择性地组合所选择的寄存器和基本加偏移值以产生有助于确定绝对地址的转换表条目的地址。该确定包括执行前缀，加窗，分区和存储器开始中的一个或多个。从转换起始寄存器到加法器的表示到逻辑电路的转换表项的输出的系统的等待时间最多为一个时钟周期。

2. 发明授权

US5652853A Multi-zone relocation facility computer memory system 失效
标题翻译：多区域搬迁设施计算机存储系统
公开(公告)号：US5652853A
公开(公告)日：1997-07-29
申请号：US455818
申请日：1995-05-31
申请人： Karl Jean Duvalsaint , Peter Hermon Gum , Moon Ju Kim , Barry Watson Krumm , Donald William McCauley , John Fenton Scanlon
发明人： Karl Jean Duvalsaint , Peter Hermon Gum , Moon Ju Kim , Barry Watson Krumm , Donald William McCauley , John Fenton Scanlon
IPC分类号： G06F9/46 , G06F12/02 , G06F12/08 , G06F12/10
CPC分类号： G06F12/0284
摘要： A memory reconfiguration system now allows a guest's absolute storage space to be mapped to multiple discontiguous host absolute storage space. A multi-zone relocation facility is provided for relocating multiple zones of the memory of the computer system. A control program being executed in its data processing system to reconfigure storages that are assigned to guests when sufficient real addressing capability is not available to provide a range of holes in the host absolute addressing space. Memory can be reconfigured by a control program that allows main storage, and expanded storage associated with a guest's real storage to be mapped to multiple discontiguous areas of host absolute spaces. When sufficient real addressing is not available in the host absolute addressing space it allows expansion of the host absolute storage space that maps a guest storage. The system can be used in scalar, parallel and massively parallel computer systems having plural logical processors (LPARs).
摘要翻译：内存重新配置系统现在允许将访客的绝对存储空间映射到多个不连续的主机绝对存储空间。提供了多区域搬迁设施，用于重新定位计算机系统的存储器的多个区域。在其数据处理系统中正在执行的控制程序，以在足够的实际寻址能力不可用于在主机绝对寻址空间中提供一系列空穴时重新配置分配给客人的存储。存储器可以由允许主存储的控制程序重新配置，并且与客人的真实存储相关联的扩展存储被映射到主机绝对空间的多个不连续的区域。当主机绝对寻址空间中没有足够的实际寻址时，它可以扩展映射guest虚拟机存储的主机绝对存储空间。该系统可用于具有多个逻辑处理器（LPAR）的标量，并行和大规模并行计算机系统。

3. 发明授权

US5649140A System for use in translating virtual addresses into absolute addresses 失效
标题翻译：用于将虚拟地址转换为绝对地址的系统
公开(公告)号：US5649140A
公开(公告)日：1997-07-15
申请号：US414671
申请日：1995-03-31
申请人： Karl Jean Duvalsaint , Mark Steven Farrell , Barry Watson Krumm , Donald William McCauley , Charles Franklin Webb
发明人： Karl Jean Duvalsaint , Mark Steven Farrell , Barry Watson Krumm , Donald William McCauley , Charles Franklin Webb
IPC分类号： G06F12/10 , G06F9/26 , G06F9/34 , G06F12/00 , G06F12/02
CPC分类号： G06F12/109 , G06F12/10
摘要： In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.
摘要翻译：在处理系统中，在虚拟地址和绝对地址之间便于翻译。该系统包括多个寄存器和用第一组地址转换参数加载它们的机制。加法器将平移原点寄存器与偏移寄存器相加以产生基准加偏移值。逻辑电路选择性地组合所选择的寄存器和基本加偏移值以产生有助于确定绝对地址的转换表条目的地址。该确定包括执行前缀，加窗，分区和存储器开始中的一个或多个。从转换起始寄存器到加法器的表示到逻辑电路的转换表项的输出的系统的等待时间最多为一个时钟周期。

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