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1. 发明申请

US20140229906A1 SIGNAL SELECTION APPARATUS AND SYSTEM, AND CIRCUIT EMULATOR AND METHOD AND PROGRAM 审中-公开
标题翻译：信号选择装置和系统以及电路仿真器及方法与程序
公开(公告)号：US20140229906A1
公开(公告)日：2014-08-14
申请号：US14252867
申请日：2014-04-15
申请人： KOHEI HOSOKAWA
发明人： KOHEI HOSOKAWA
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G01R31/318342 , G06F2217/10 , G06F2217/78 , G06F2217/84
摘要： Disclosed is a system in which in order to obtain the operation parameter of a circuit based on an implementable area indicating a circuit scale that can be implemented on a circuit implementation device, circuit area information, and operation parameter measuring circuit area information, an observation signal number determining means determines observation signal information on a circuit that obtains the operation parameter of the circuit. The number of the extracted signals is determined in view of the area that can be implemented on a digital LSI or an emulator and the area of the circuit to be implemented (refer to FIG. 1).
摘要翻译：公开了一种系统，其中为了基于指示可以在电路实现装置上实现的电路规模的可实现区域获得电路的操作参数，电路区域信息和操作参数测量电路区域信息，观察信号数字确定装置确定获得电路的操作参数的电路上的观测信号信息。考虑到可以在数字LSI或仿真器上实现的区域和要实现的电路的区域（参见图1）来确定提取的信号的数量。

2. 发明授权

US08683404B2 Semiconductor verification apparatus, method, and program 有权
标题翻译：半导体验证装置，方法和程序
公开(公告)号：US08683404B2
公开(公告)日：2014-03-25
申请号：US13056092
申请日：2009-04-20
申请人： Kohei Hosokawa
发明人： Kohei Hosokawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A memory is provided for storing a control sequence of a clock cycle for each semiconductor device. The program sequence is calculated in advance and written in the memory by a program etc. on a computer. When the relevant semiconductor device is controlled, the contents of the memory are provided to the semiconductor device.
摘要翻译：提供存储器，用于存储每个半导体器件的时钟周期的控制序列。程序序列预先计算并通过计算机上的程序等写入存储器中。当相关半导体器件被控制时，存储器的内容被提供给半导体器件。

3. 发明申请

US20130105607A1 PULVERIZING APPARATUS 审中-公开
公开(公告)号：US20130105607A1
公开(公告)日：2013-05-02
申请号：US13696101
申请日：2011-04-28
申请人： Masahiro Yoshikawa , Takashi Shibata , Kohei Hosokawa
发明人： Masahiro Yoshikawa , Takashi Shibata , Kohei Hosokawa
IPC分类号： B02C13/288
CPC分类号： B02C13/288 , B02C17/163 , B02C17/166 , B02C17/1815 , B02C17/188 , B02C17/22
摘要： A pulverizing apparatus for processing a powder material that can be readily melted by friction heat generated between the pulverizing apparatus and the material. The pulverizing apparatus includes a casing (2) having a cylindrical inner face, a rotor (10) driven to rotate about the axis X of the casing and having a rugged portion (10G) in its outer periphery, a gas source providing a gas flow for conveying the powder material from a feed opening (3) provided at an end of the casing along the an axial direction to a discharge opening (4) provided at the other axial end of the casing, a coolant source providing coolant to flow in a coolant passage (15) formed inside the rotor. The rugged portion is divided along the axial direction by an annular cutout portion (11) extending along the peripheral direction of the rotor.
摘要翻译：一种用于加工粉碎材料的粉碎装置，其可以通过在粉碎装置和材料之间产生的摩擦热容易地熔化。粉碎装置包括具有圆筒形内表面的壳体（2），被驱动为围绕壳体的轴线X旋转并且在其外周具有凹凸部分（10G）的转子（10），提供气流用于将设置在壳体的端部处的进料口（3）沿轴向方向输送到设置在壳体的另一轴向端部处的排出口（4），冷却剂源提供冷却剂以在冷却剂通道（15）形成在转子内部。凹凸部沿着轴向沿着沿着转子的圆周方向延伸的环形切口部分（11）分开。

4. 发明授权

US08510691B2 Semiconductor verification apparatus, method and program 有权
标题翻译：半导体验证装置，方法和程序
公开(公告)号：US08510691B2
公开(公告)日：2013-08-13
申请号：US13120622
申请日：2009-10-08
申请人： Kohei Hosokawa
发明人： Kohei Hosokawa
IPC分类号： G06F17/50
CPC分类号： G01R31/318516
摘要： A semiconductor device which can only load a logical value of an arbitrary memory element is rendered possible to allow a logical value of an arbitrary signal to be loaded at a high speed. A circuit diagram of the semiconductor device is input and a memory element required for calculating a desired signal is detected. The logical value of the memory element is loaded from the semiconductor device, and the logical value of the desired signal is determined in accordance with the logical value of the memory element and the circuit configuration.
摘要翻译：只能加载任意存储元件的逻辑值的半导体器件可以允许以高速加载任意信号的逻辑值。输入半导体器件的电路图，并检测计算所需信号所需的存储元件。从半导体器件加载存储元件的逻辑值，并根据存储元件的逻辑值和电路配置来确定期望信号的逻辑值。

5. 发明申请

US20110191735A1 SEMICONDUCTOR VERIFICATION APPARATUS, METHOD AND PROGRAM 有权
标题翻译：半导体验证装置，方法和程序
公开(公告)号：US20110191735A1
公开(公告)日：2011-08-04
申请号：US13120622
申请日：2009-10-08
申请人： Kohei Hosokawa
发明人： Kohei Hosokawa
IPC分类号： G06F17/50
CPC分类号： G01R31/318516
摘要： A semiconductor device which can only load a logical value of an arbitrary memory element is rendered possible to allow a logical value of an arbitrary signal to be loaded at a high speed. A circuit diagram of the semiconductor device is input and a memory element required for calculating a desired signal is detected. The logical value of the memory element is loaded from the semiconductor device, and the logical value of the desired signal is determined in accordance with the logical value of the memory element and the circuit configuration.
摘要翻译：只能加载任意存储元件的逻辑值的半导体器件可以允许以高速加载任意信号的逻辑值。输入半导体器件的电路图，并检测计算所需信号所需的存储元件。从半导体器件加载存储元件的逻辑值，并根据存储元件的逻辑值和电路配置来确定期望信号的逻辑值。

6. 发明授权

US07876575B2 Substrate housing container 失效
标题翻译：基材容器
公开(公告)号：US07876575B2
公开(公告)日：2011-01-25
申请号：US12147045
申请日：2008-06-26
申请人： Kohei Hosokawa
发明人： Kohei Hosokawa
IPC分类号： H05K7/18 , H05K7/14
CPC分类号： H01L21/67383
摘要： The present invention includes a ceiling portion 8, bottom portion 9, a substrate housing portion 3 formed by a side walls 5 to 7, a plurality of wafer slots 11 arrayed in parallel on the inner surface of the side walls 6 and 7, a slit portion 12 formed in an extended manner along the array direction of the wafer slots 11 on each of a second side wall 6 and a third side wall 7, a slide portion 18 movably arrayed along each of the slit portions 12, a plurality of substrate securing pieces arrayed with substantially the same intervals with the intervals of the wafer slots 11 on the inner surface of the slide portion 18, in which, with the slide portion being in a substrate securing position, the substrate housing pieces press and secure the substrate on the wafer slot 11, and in a substrate securing releasing position, the substrate housing pieces move separately from a circumferential portion of the substrate and releases a securing state of the substrate. In accordance with the present invention, it is possible to provide a substrate housing container which is able to hold the wafer in a predetermined position even in a case in which the substrate housing container is moved in which a lid body is released.
摘要翻译：本发明包括顶部8，底部9，由侧壁5至7形成的基板收纳部分3，平行于侧壁6和7的内表面上排列的多个晶片槽11，狭缝在第二侧壁6和第三侧壁7中的每一个上沿着晶片槽11的排列方向延伸形成的部分12，沿着每个狭缝部分12可移动地排列的滑动部分18，多个基板固定以与滑动部分18的内表面上的晶片槽11的间隔大致相同的间隔排列的片，其中，当滑动部分处于基板固定位置时，基板壳体件将基板压紧晶片槽11，并且在基板固定解除位置中，基板壳体件与基板的圆周部分分开移动并释放基板的固定状态。根据本发明，可以提供一种能够将晶片保持在预定位置的基板容纳容器，即使在其中释放盖体的基板容纳容器被移动的情况下也是如此。

7. 发明授权

US08739107B2 Signal selection apparatus and system, and circuit emulator and method and program 有权
标题翻译：信号选择装置及系统，电路仿真器及方法与程序
公开(公告)号：US08739107B2
公开(公告)日：2014-05-27
申请号：US12521606
申请日：2007-11-30
申请人： Kohei Hosokawa
发明人： Kohei Hosokawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G01R31/318342 , G06F2217/10 , G06F2217/78 , G06F2217/84
摘要： Disclosed is a system in which in order to obtain the operation parameter of a circuit based on an implementable area indicating a circuit scale that can be implemented on a circuit implementation device, circuit area information, and operation parameter measuring circuit area information, an observation signal number determining means determines observation signal information on a circuit that obtains the operation parameter of the circuit. The number of the extracted signals is determined in view of the area that can be implemented on a digital LSI or an emulator and the area of the circuit to be implemented (refer to FIG. 1).
摘要翻译：公开了一种系统，其中为了基于指示可以在电路实现装置上实现的电路规模的可实现区域获得电路的操作参数，电路区域信息和操作参数测量电路区域信息，观察信号数字确定装置确定获得电路的操作参数的电路上的观测信号信息。考虑到可以在数字LSI或仿真器上实现的区域和要实现的电路的区域（参见图1）来确定提取的信号的数量。

8. 发明申请

US20100198573A1 SIGNAL SELECTING APPARATUS, CIRCUIT AMENDING APPARATUS, CIRCUIT SIMULATOR, CIRCUIT EMULATOR, METHOD OF SIGNAL SELECTION AND PROGRAM 有权
标题翻译：信号选择装置，电路修正装置，电路仿真器，电路仿真器，信号选择方法及程序
公开(公告)号：US20100198573A1
公开(公告)日：2010-08-05
申请号：US12311249
申请日：2007-09-25
申请人： Kohei Hosokawa
发明人： Kohei Hosokawa
IPC分类号： G06F19/00 , G06F17/50
CPC分类号： G06F17/5018 , G06F2217/10
摘要： Signal selecting apparatus 100 according to the present invention for determining an operation parameter of circuit 101 includes circuit analyzing means 110 for enumerating signals in the circuit that are to be measured for the operation parameter when information of the circuit is input thereto, observation signal number determination means 111 for statistically determining the number of observation signals required to determine the operation parameter from the width and reliability of an estimated error and from the number of enumerated signals, and observation signal selecting means 112 for selecting, from the enumerated signals, the same number of signals as the number of observation signals.
摘要翻译：根据本发明的用于确定电路101的操作参数的信号选择装置100包括电路分析装置110，用于当输入电路的信息时，对用于操作参数的电路中的信号进行枚举，观察信号数确定用于根据估计误差的宽度和可靠性以及从枚举信号的数量统计确定确定操作参数所需的观测信号的数量的装置111以及用于从枚举的信号中选择相同数目的观测信号选择装置112 的信号作为观测信号的数量。

9. 发明申请

US20090002966A1 SUBSTRATE HOUSING CONTAINER 失效
标题翻译：基座容器
公开(公告)号：US20090002966A1
公开(公告)日：2009-01-01
申请号：US12147045
申请日：2008-06-26
申请人： Kohei Hosokawa
发明人： Kohei Hosokawa
IPC分类号： H05K7/02
CPC分类号： H01L21/67383
摘要： The present invention includes a ceiling portion 8, bottom portion 9, a substrate housing portion 3 formed by a side walls 5 to 7, a plurality of wafer slots 11 arrayed in parallel on the inner surface of the side walls 6 and 7, a slit portion 12 formed in an extended manner along the array direction of the wafer slots 11 on each of a second side wall 6 and a third side wall 7, a slide portion 18 movably arrayed along each of the slit portions 12, a plurality of substrate securing pieces arrayed with substantially the same intervals with the intervals of the wafer slots 11 on the inner surface of the slide portion 18, in which, with the slide portion being in a substrate securing position, the substrate housing pieces press and secure the substrate on the wafer slot 11, and in a substrate securing releasing position, the substrate housing pieces move separately from a circumferential portion of the substrate and releases a securing state of the substrate. In accordance with the present invention, it is possible to provide a substrate housing container which is able to hold the wafer in a predetermined position even in a case in which the substrate housing container is moved in which a lid body is released.
摘要翻译：本发明包括顶部8，底部9，由侧壁5至7形成的基板收纳部分3，平行于侧壁6和7的内表面上排列的多个晶片槽11，狭缝在第二侧壁6和第三侧壁7中的每一个上沿着晶片槽11的排列方向延伸形成的部分12，沿着每个狭缝部分12可移动地排列的滑动部分18，多个基板固定以与滑动部分18的内表面上的晶片槽11的间隔大致相同的间隔排列的片，其中，当滑动部分处于基板固定位置时，基板壳体件将基板压紧晶片槽11，并且在基板固定解除位置中，基板壳体件与基板的圆周部分分开移动并释放基板的固定状态。根据本发明，可以提供一种能够将晶片保持在预定位置的基板容纳容器，即使在其中释放盖体的基板容纳容器被移动的情况下也是如此。

10. 发明授权

US07228513B2 Circuit operation verification device and method 有权
标题翻译：电路运行验证装置及方法
公开(公告)号：US07228513B2
公开(公告)日：2007-06-05
申请号：US10935271
申请日：2004-09-08
申请人： Kohei Hosokawa
发明人： Kohei Hosokawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A circuit verification device includes emulators to which circuit portions obtained by dividing the circuit are implemented. The emulators communicate with each other through a bus to verify the functional operation of the circuit. The circuit is divided based on a communication occurrence pattern between circuit units so that the number of communications occurring between circuit portions is minimized. The input signals of the bus are preferably arranged in the bus address space in descending order of a signal change rate, and a burst transfer may be utilized. Through paths within the circuit being verified are searched, and a plurality of circuit units is divided so as to minimize the number of through paths among the circuit portions.
摘要翻译：电路验证装置包括实现通过划分电路获得的电路部分的仿真器。仿真器通过总线相互通信，以验证电路的功能操作。基于电路单元之间的通信发生模式来分割电路，使得在电路部分之间发生的通信的数量最小化。总线的输入信号优选地以信号变化率的降序布置在总线地址空间中，并且可以利用突发传送。搜索正在验证的电路内的通路，分割多个电路单元以使电路部分之间的通路数量最小化。

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