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    • 4. 发明申请
    • Differential amplifier circuit operable with wide range of input voltages
    • 差分放大器电路可在宽范围的输入电压下工作
    • US20070146063A1
    • 2007-06-28
    • US11360602
    • 2006-02-24
    • Junko NakamotoNaoaki Naka
    • Junko NakamotoNaoaki Naka
    • G06G7/12
    • H03F3/45183H03F3/4521H03F2203/45691H03F2203/45702
    • A differential amplifier circuit includes a first load coupled to a first reference potential, a first MOS transistor having a drain node coupled to the first load, a second load coupled to the first reference potential, a second MOS transistor having a drain node coupled to the second load, a first constant current source coupled between a second reference potential and the source nodes of the first MOS transistor and the second MOS transistor, a third MOS transistor having a source node coupled to the first load, a fourth MOS transistor having a source node the second load, and a second constant current source coupled between the second reference potential and the drain nodes of the third MOS transistor and the fourth MOS transistor, wherein the first and second MOS transistors are of a first conduction type, and the third and fourth MOS transistors are of a second conduction type.
    • 差分放大器电路包括耦合到第一参考电位的第一负载,具有耦合到第一负载的漏极节点的第一MOS晶体管,耦合到第一参考电位的第二负载,具有耦合到第一参考电位的漏极节点的第二MOS晶体管 第二负载,耦合在第二参考电位和第一MOS晶体管和第二MOS晶体管的源节点之间的第一恒定电流源,具有耦合到第一负载的源极点的第三MOS晶体管,具有源极的第四MOS晶体管 节点第二负载,以及耦合在第三MOS晶体管和第四MOS晶体管的第二参考电位和漏极节点之间的第二恒流源,其中第一和第二MOS晶体管是第一导电类型,并且第三和 第四MOS晶体管是第二导电类型。
    • 7. 发明授权
    • High precision data and clock output circuit
    • 高精度数据和时钟输出电路
    • US07003060B2
    • 2006-02-21
    • US10095945
    • 2002-03-13
    • Naoaki NakaJunko Nakamoto
    • Naoaki NakaJunko Nakamoto
    • H04L7/00
    • H03K3/0375
    • An output circuit of the present invention includes a data output circuit and a clock output circuit. The output circuit includes a first D-type flip-flop and a selector for selectively outputting an output from the first D-type flip-flop or second data according to a selection signal. The clock output circuit includes a second D-type flip-flop, a third D-type flip-flop, and a dummy selector circuit. The dummy selector circuit is connected to the second and third D-type flip-flops and outputs a clock signal by using the same elements as those of the selector in order to realize the same delay time as that of the selector.
    • 本发明的输出电路包括数据输出电路和时钟输出电路。 输出电路包括第一D型触发器和选择器,用于根据选择信号选择性地输出来自第一D型触发器的输出或第二数据。 时钟输出电路包括第二D型触发器,第三D型触发器和虚拟选择电路。 虚拟选择器电路连接到第二和第三D型触发器,并且通过使用与选择器相同的元件输出时钟信号,以便实现与选择器相同的延迟时间。
    • 8. 发明授权
    • Differential output circuit
    • 差分输出电路
    • US07825694B2
    • 2010-11-02
    • US12551978
    • 2009-09-01
    • Toshie KatohJunko Nakamoto
    • Toshie KatohJunko Nakamoto
    • H03K19/094
    • H03K19/018528
    • A differential output circuit including a first output driving circuit that includes a first PMOS transistor and a first NMOS transistor connected in series to each other, a second output driving circuit that includes a second PMOS transistor and a second NMOS transistor connected in series to each other and a control circuit, wherein, when a control signal has a first value, the control circuit selectively turns on one of the first and second PMOS transistors and selectively turns on one of the first and second NMOS transistors, thereby controlling the first and second output driving circuits to output a first pair of differential signals, and when the control signal has a second value, the control circuit supplies no current to the PMOS transistors and selectively turns on one of the NMOS transistors, thereby controlling the output driving circuits to output a second pair of differential signals.
    • 一种差分输出电路,包括:第一输出驱动电路,包括彼此串联连接的第一PMOS晶体管和第一NMOS晶体管;第二输出驱动电路,包括彼此串联连接的第二PMOS晶体管和第二NMOS晶体管; 以及控制电路,其中,当控制信号具有第一值时,所述控制电路选择性地接通所述第一和第二PMOS晶体管中的一个,并选择性地导通所述第一和第二NMOS晶体管中的一个,从而控制所述第一和第二输出 驱动电路输出第一对差分信号,并且当控制信号具有第二值时,控制电路不向PMOS晶体管提供电流,并选择性地导通NMOS晶体管中的一个,从而控制输出驱动电路输出 第二对差分信号。