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1. 发明授权

US08312340B2 Information processing device, data transmitting device, and data transfer method of data transmitting device 失效
标题翻译：数据发送装置的信息处理装置，数据发送装置以及数据传送方法
公开(公告)号：US08312340B2
公开(公告)日：2012-11-13
申请号：US12926690
申请日：2010-12-03
申请人： Shintaro Itozawa , Hiroshi Nakayama , Junji Ichimiya
发明人： Shintaro Itozawa , Hiroshi Nakayama , Junji Ichimiya
IPC分类号： H03M13/00 , H04L1/18
CPC分类号： H04L1/007 , G06F11/0724 , G06F11/0763 , H04L1/0009 , H04L1/0057 , H04L25/14
摘要： A selection-signal generating circuit in an LSI being a transmission-side LSI, when a transmission error is detected on an A-side signal line and degeneration control is performed thereon, instructs a selector to select an input from an ECC generator in order to transmit data and ECC data for this data to be transmitted via the B-side signal line, via the A-side signal line. In this manner, the degenerated signal line is used to transmit the ECC data for transmission data to be transmitted via a signal line which is not degenerated.
摘要翻译：作为发送侧LSI的LSI中的选择信号生成电路，当在A侧信号线上检测到发送错误并进行退化控制时，指示选择器从ECC发生器选择输入，以便通过A侧信号线经由B侧信号线发送该数据的数据和ECC数据。以这种方式，退化的信号线用于发送经由不退化的信号线发送的发送数据的ECC数据。

2. 发明授权

US07913028B2 Data processing system having multiplexed data relaying devices, data processing aparatus having multiplexed data relaying devices, and a method of incorporating data relaying devices in data processing system having multiplexed data relaying devices 有权
标题翻译：具有复用数据中继装置的数据处理系统，具有复用数据中继装置的数据处理装置，以及将数据中继装置并入具有复用数据中继装置的数据处理系统中的方法
公开(公告)号：US07913028B2
公开(公告)日：2011-03-22
申请号：US11785903
申请日：2007-04-20
申请人： Takayuki Kinoshita , Junji Ichimiya , Shintaro Itozawa , Koichi Odahara
发明人： Takayuki Kinoshita , Junji Ichimiya , Shintaro Itozawa , Koichi Odahara
IPC分类号： G06F13/00 , G06F11/16
CPC分类号： G06F13/4022
摘要： When a new data relaying device that has yet to have configuration information set therein is incorporated, the configuration information of an existing data relaying device is copied to the new data relaying device.
摘要翻译：当并入尚未配置其中的配置信息的新数据中继设备时，将现有数据中继设备的配置信息复制到新的数据中继设备。

3. 发明授权

US07802041B2 Information processing apparatus including transfer device for transferring requests 有权
标题翻译：信息处理装置，包括用于传送请求的传送装置
公开(公告)号：US07802041B2
公开(公告)日：2010-09-21
申请号：US12219627
申请日：2008-07-24
申请人： Takayuki Kinoshita , Junji Ichimiya
发明人： Takayuki Kinoshita , Junji Ichimiya
IPC分类号： G06F12/00 , G06F13/14 , G06F13/00 , G06F15/76
CPC分类号： G06F11/1679
摘要： According to an aspect of an embodiment, an apparatus has a pair of first system boards, each of the first system boards including a processor and being adapted for sending duplicate requests, in parallel, respectively, a second system board including a processor and being adapted for sending requests, a first transfer device for transferring requests, having a first arbiter for selecting and outputting one of the duplicate requests sent from each of the first system boards, and a second arbiter for selecting and outputting one of the requests sent from the second system board and a second transfer device for transferring requests, having a third arbiter for selecting one of the duplicate requests sent from each of the first system boards and outputting the selected request in synchronization with the selected request outputted by the first arbiter, the second transfer device having a forth arbiter.
摘要翻译：根据实施例的一个方面，一种装置具有一对第一系统板，每个第一系统板包括处理器，并且适于并行地发送重复请求，第二系统板包括处理器并被适配用于发送请求的第一传送设备，具有用于选择和输出从每个第一系统板发送的一个重复请求的第一仲裁器的第一仲裁器，以及用于选择和输出从第二系统发送的请求之一的第二仲裁器系统板和用于传送请求的第二传送装置，具有用于选择从每个第一系统板发送的一个重复请求的第三仲裁器，并且与由第一仲裁器输出的所选择的请求同步地输出所选择的请求，第二传送装置具有第四仲裁器。

4. 发明申请

US20090300452A1 ERROR IDENTIFYING METHOD, DATA PROCESSING DEVICE, AND SEMICONDUCTOR DEVICE 失效
标题翻译：错误识别方法，数据处理设备和半导体器件
公开(公告)号：US20090300452A1
公开(公告)日：2009-12-03
申请号：US12396106
申请日：2009-03-02
申请人： Junji ICHIMIYA , Hiroshi NAKAYAMA , Shintarou ITOZAWA
发明人： Junji ICHIMIYA , Hiroshi NAKAYAMA , Shintarou ITOZAWA
IPC分类号： H04L1/18 , G06F11/07 , H03M13/09 , G06F11/14
CPC分类号： H03M13/09 , G06F11/1443
摘要： A data processing device which performs a data transmission between semiconductor devices using a plurality of signal lines. In the data processing device, when there occurs an error in a data transmission from a transmitting device to a receiving device using a plurality of signal lines, data in which the error has occurred is stored. The stored data is compared bit by bit with non-erroneous data, thereby designating a bit in which error has occurred in the stored data.
摘要翻译：一种使用多条信号线在半导体器件之间执行数据传输的数据处理装置。在数据处理装置中，当使用多条信号线从发送装置到接收装置的数据传输发生错误时，存储发生了错误的数据。将所存储的数据逐位地与非错误数据进行比较，从而指定存储的数据中发生错误的位。

5. 发明申请

US20080046622A1 Transmission control device and transmission control method 审中-公开
标题翻译：变速箱控制装置及变速箱控制方式
公开(公告)号：US20080046622A1
公开(公告)日：2008-02-21
申请号：US11785409
申请日：2007-04-17
申请人： Takayuki Kinoshita , Junji Ichimiya , Shintarou Itozawa
发明人： Takayuki Kinoshita , Junji Ichimiya , Shintarou Itozawa
IPC分类号： G06F13/24
CPC分类号： G06F13/4022 , G06F13/4031
摘要： An address crossbar switch temporarily buffers received requests while monitoring the requests, and counts requests of a predetermined type (for example, long-packet address requests). When a counter value exceeds a predetermined threshold value (for example, when a long-packet counter value exceeds 100), the address crossbar switch suspends broadcasting the address requests for a predetermined time period. After the predetermined time period has elapsed, the address crossbar switch restarts broadcasting the address requests in the order in which they were received.
摘要翻译：在监视请求的同时，地址交叉开关临时缓冲所接收的请求，并计数预定类型的请求（例如，长包地址请求）。当计数器值超过预定阈值时（例如，当长分组计数器值超过100时），地址交叉开关暂停在预定时间段内广播地址请求。在预定时间段过去之后，地址交叉开关按照接收的顺序重新播放地址请求。

6. 发明申请

US20090031064A1 Information processing apparatus including transfer device for transferring requests 有权
标题翻译：信息处理装置，包括用于传送请求的传送装置
公开(公告)号：US20090031064A1
公开(公告)日：2009-01-29
申请号：US12219627
申请日：2008-07-24
申请人： Takayuki Kinoshita , Junji Ichimiya
发明人： Takayuki Kinoshita , Junji Ichimiya
IPC分类号： G06F13/42 , G06F13/20
CPC分类号： G06F11/1679
摘要： According to an aspect of an embodiment, an apparatus has a pair of first system boards, each of the first system boards including a processor and being adapted for sending duplicate requests, in parallel, respectively, a second system board including a processor and being adapted for sending requests, a first transfer device for transferring requests, having a first arbiter for selecting and outputting one of the duplicate requests sent from each of the first system boards, and a second arbiter for selecting and outputting one of the requests sent from the second system board and a second transfer device for transferring requests, having a third arbiter for selecting one of the duplicate requests sent from each of the first system boards and outputting the selected request in synchronization with the selected request outputted by the first arbiter, the second transfer device having a forth arbiter.
摘要翻译：根据实施例的一个方面，一种装置具有一对第一系统板，每个第一系统板包括处理器，并且适于并行地发送重复请求，第二系统板包括处理器并被适配用于发送请求的第一传送设备，具有用于选择和输出从每个第一系统板发送的一个重复请求的第一仲裁器的第一仲裁器，以及用于选择和输出从第二系统发送的请求之一的第二仲裁器系统板和用于传送请求的第二传送装置，具有用于选择从每个第一系统板发送的一个重复请求的第三仲裁器，并且与由第一仲裁器输出的所选择的请求同步地输出所选择的请求，第二传送装置具有第四仲裁器。

7. 发明申请

US20060218519A1 Layout design method for semiconductor integrated circuit, and semiconductor integrated circuit 有权
标题翻译：半导体集成电路的布局设计方法和半导体集成电路
公开(公告)号：US20060218519A1
公开(公告)日：2006-09-28
申请号：US11440633
申请日：2006-05-24
申请人： Junji Ichimiya
发明人： Junji Ichimiya
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： In a layout design method for a semiconductor integrated circuit, a cell layout library is provided which stores structure information of functional cells and a plurality of groups of filler cells, each filler cell acting to fill space between the functional cells. The functional cells are arranged on a layout based on the structural information from the layout library. The filler cells of any of the plurality of groups are arranged selectively based on the structural information from the layout library so that the filler cells are arranged in channel regions where the functional cells are not located on the layout, each channel region being located at a predetermined distance from signal lines on the layout.
摘要翻译：在半导体集成电路的布局设计方法中，提供存储功能单元和多组填充单元的结构信息的单元布局库，每个填充单元用于填充功能单元之间的空间。功能单元基于来自布局库的结构信息布置在布局上。多个组中的任一组的填充单元基于来自布局库的结构信息选择性地布置，使得填充单元布置在功能单元不位于布局上的通道区域中，每个通道区域位于与布局上的信号线预定距离。

8. 发明授权

US08516291B2 Information processing apparatus, data reception device and method of controlling the information processing apparatus 失效
标题翻译：信息处理装置，数据接收装置以及信息处理装置的控制方法
公开(公告)号：US08516291B2
公开(公告)日：2013-08-20
申请号：US12955473
申请日：2010-11-29
申请人： Hiroshi Nakayama , Junji Ichimiya , Shintaro Itozawa
发明人： Hiroshi Nakayama , Junji Ichimiya , Shintaro Itozawa
IPC分类号： G06F1/12
CPC分类号： G06F13/4072
摘要： A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP value so as to output an adjusted clock signal. By synchronizing transmission data with the adjusted clock signal, reception data is generated. A data adjustment circuit delays the transmission data on the basis of a TAP2 value. By synchronizing the delayed transmission data with the adjusted clock signal, adjusted reception data is generated. A data adjustment control circuit generates the TAP2 value on the basis of a result of a comparison between the reception data and the adjusted reception data, and outputs to a clock adjustment control circuit an instruction to update the TAP value.
摘要翻译：时钟调整电路基于TAP值延迟时钟信号的相位，以输出调整后的时钟信号。通过将发送数据与调整后的时钟信号同步，生成接收数据。数据调整电路基于TAP2值来延迟发送数据。通过将经延迟的发送数据与经调整的时钟信号同步，生成经调整的接收数据。数据调整控制电路根据接收数据和调整接收数据的比较结果，生成TAP2值，并向时钟调整控制电路输出更新TAP值的指示。

9. 发明授权

US08401139B2 Data transfer unit, data transmission device, data receiving device, and control method 失效
标题翻译：数据传输单元，数据传输设备，数据接收设备和控制方法
公开(公告)号：US08401139B2
公开(公告)日：2013-03-19
申请号：US13137670
申请日：2011-09-01
申请人： Shintaro Itozawa , Hiroshi Nakayama , Junji Ichimiya , Daisuke Itou
发明人： Shintaro Itozawa , Hiroshi Nakayama , Junji Ichimiya , Daisuke Itou
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , G06F1/10 , H04L7/0008 , H04L7/0037 , H04L7/04
摘要： A transmission LSI calculates a buffer usage rate in accordance with data stored in a buffer in a transmission data processing unit and determines, in accordance with the calculated buffer usage rate, the number of signal lines that perform a phase readjustment and the timing thereof. Then, the transmission LSI and a receiving LSI perform a phase adjustment using some of the signal lines and continues a data transfer using the rest of the signal lines. Accordingly, it is possible to maintain the optimum phase of a clock without delaying the data transfer.
摘要翻译：发送LSI根据存储在发送数据处理单元中的缓冲器中的数据来计算缓冲器使用率，并且根据计算的缓冲器使用率确定进行相位重新调整的信号线的数量及其定时。然后，传输LSI和接收LSI使用一些信号线进行相位调整，并使用剩余的信号线继续进行数据传送。因此，可以保持时钟的最佳相位而不延迟数据传送。

10. 发明申请

US20110309868A1 Data transfer unit, data transmission device, data receiving device, and control method 失效
标题翻译：数据传输单元，数据传输设备，数据接收设备和控制方法
公开(公告)号：US20110309868A1
公开(公告)日：2011-12-22
申请号：US13137670
申请日：2011-09-01
申请人： Shintaro ITOZAWA , Hiroshi NAKAYAMA , Junji ICHIMIYA , Daisuke ITOU
发明人： Shintaro ITOZAWA , Hiroshi NAKAYAMA , Junji ICHIMIYA , Daisuke ITOU
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , G06F1/10 , H04L7/0008 , H04L7/0037 , H04L7/04
摘要： A transmission LSI calculates a buffer usage rate in accordance with data stored in a buffer in a transmission data processing unit and determines, in accordance with the calculated buffer usage rate, the number of signal lines that perform a phase readjustment and the timing thereof. Then, the transmission LSI and a receiving LSI perform a phase adjustment using some of the signal lines and continues a data transfer using the rest of the signal lines. Accordingly, it is possible to maintain the optimum phase of a clock without delaying the data transfer.
摘要翻译：发送LSI根据存储在发送数据处理单元中的缓冲器中的数据来计算缓冲器使用率，并且根据计算的缓冲器使用率确定进行相位重新调整的信号线的数量及其定时。然后，传输LSI和接收LSI使用一些信号线进行相位调整，并使用剩余的信号线继续进行数据传送。因此，可以保持时钟的最佳相位而不延迟数据传送。

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