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    • 1. 发明授权
    • Digital filter having a switching matrix and adders
    • 具有开关矩阵和加法器的数字滤波器
    • US5212660A
    • 1993-05-18
    • US760324
    • 1991-09-16
    • Junichi Orihara
    • Junichi Orihara
    • H03H17/06
    • H03H17/06
    • In a digital filter, a plurality of delay elements D.sub.1 -D.sub.n are serially connected to one another, and taps for obtaining delay signals being different in delay time from one another are provided at respective connecting portions. Outputs from a plurality of multipliers M.sub.0 -M.sub.3 are added together by an adder A, and the result is outputted to an output terminal of the digital filter. Signal selecting means S.sub.00 -S.sub.3n are switched on or off between the plurality of taps and the input terminals of the plurality of multipliers. The multipliers M.sub.0 -M.sub.3 can be connected to optional taps, and, by use of a relatively small number of multipliers, a plurality of delay signals being different in delay time from one another are formed into a composite output signal while the delay times and the signal levels being widely selected.
    • 在数字滤波器中,多个延迟元件D1-Dn彼此串联连接,并且在相应的连接部分处提供用于获得彼此延迟时间不同的延迟信号的抽头。 来自多个乘法器M0-M3的输出由加法器A相加在一起,结果输出到数字滤波器的输出端。 在多个抽头和多个乘法器的输入端子之间接通或断开信号选择装置S00-S3n。 乘法器M0-M3可以连接到可选的抽头,并且通过使用相对较少数量的乘法器,彼此延迟时间不同的多个延迟信号被形成为复合输出信号,而延迟时间和 信号电平被广泛选择。