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1. 发明授权

US08518790B2 Method of forming memory device 有权
标题翻译：形成存储器件的方法
公开(公告)号：US08518790B2
公开(公告)日：2013-08-27
申请号：US13692329
申请日：2012-12-03
申请人： Jung-in Kim , Jae-Hee Oh , Hyunho Kim , Ji-Hyun Jeong
发明人： Jung-in Kim , Jae-Hee Oh , Hyunho Kim , Ji-Hyun Jeong
IPC分类号： H01L21/02
CPC分类号： H01L45/16 , H01L27/1021 , H01L27/24
摘要： A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.
摘要翻译：一种可变电阻存储器件及其形成方法。该方法可以包括在衬底上形成下电极，在衬底上堆叠第一蚀刻停止层和第二蚀刻停止层，在第二蚀刻停止层上形成绝缘层，形成凹陷区域以通过图案曝光下电极绝缘层和第一和第二蚀刻停止层，在凹陷区域中形成可变电阻材料层，并在可变电阻材料层上形成上电极。第一蚀刻停止层可以相对于第二蚀刻停止层具有蚀刻选择性。

2. 发明授权

US08275059B2 Frequency synchronization apparatus and method in OFDM system 失效
标题翻译： OFDM系统中的频率同步装置和方法
公开(公告)号：US08275059B2
公开(公告)日：2012-09-25
申请号：US12477269
申请日：2009-06-03
申请人： Bon Young Koo , Hyung Jin Choi , Se Bin Im , Jung In Kim
发明人： Bon Young Koo , Hyung Jin Choi , Se Bin Im , Jung In Kim
IPC分类号： H04L27/28
CPC分类号： H04L27/2657 , H04L27/2676 , H04L27/2688
摘要： A frequency synchronization apparatus includes: a correlating unit that obtains a first correlation value by correlating a known reference guard interval of an OFDM symbol and a reference copy interval corresponding to the reference guard interval, and obtains a second correlation value by correlating the estimate guard interval and an estimate copy interval corresponding to the estimate guard interval; a determining unit that compares the first and second correlation values to determine a first case where the first correlation value is larger by a pre-set magnification than the second correlation value, a second case where the second correlation value is larger by a pre-set magnification than the first correlation value, and a third case which is not the first case nor the second case; and a frequency offset estimating unit that estimates a frequency offset by using a correlation value corresponding to any one of the first to third.
摘要翻译：频率同步装置包括：相关单元，通过将OFDM符号的已知参考保护间隔与对应于参考保护间隔的参考复制间隔相关联来获得第一相关值，并且通过将估计保护间隔以及对应于估计保护间隔的估计复制间隔; 确定单元，其比较所述第一和第二相关值，以确定所述第一相关值比所述第二相关值大预定倍数的第一情况，所述第二相关值大于预设值的第二情况并且不是第一种情况的第三种情况也不是第二种情况; 以及频率偏移估计单元，其通过使用与第一至第三中的任一个相对应的相关值来估计频率偏移。

3. 发明申请

US20100227449A1 METHOD OF FORMING MEMORY DEVICE 有权
标题翻译：形成存储器件的方法
公开(公告)号：US20100227449A1
公开(公告)日：2010-09-09
申请号：US12714685
申请日：2010-03-01
申请人： Jung-in KIM , Jae-Hee Oh , Hyunho Kim , Ji-Hyun Jeong
发明人： Jung-in KIM , Jae-Hee Oh , Hyunho Kim , Ji-Hyun Jeong
IPC分类号： H01L21/02
CPC分类号： H01L45/16 , H01L27/1021 , H01L27/24
摘要： A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.
摘要翻译：一种可变电阻存储器件及其形成方法。该方法可以包括在衬底上形成下电极，在衬底上堆叠第一蚀刻停止层和第二蚀刻停止层，在第二蚀刻停止层上形成绝缘层，形成凹陷区域以通过图案曝光下电极绝缘层和第一和第二蚀刻停止层，在凹陷区域中形成可变电阻材料层，并在可变电阻材料层上形成上电极。第一蚀刻停止层可以相对于第二蚀刻停止层具有蚀刻选择性。

4. 发明授权

US08324067B2 Method of forming memory device 有权
标题翻译：形成存储器件的方法
公开(公告)号：US08324067B2
公开(公告)日：2012-12-04
申请号：US12714685
申请日：2010-03-01
申请人： Jung-in Kim , Jae-Hee Oh , Hyunho Kim , Ji-Hyun Jeong
发明人： Jung-in Kim , Jae-Hee Oh , Hyunho Kim , Ji-Hyun Jeong
IPC分类号： H01L21/02
CPC分类号： H01L45/16 , H01L27/1021 , H01L27/24
摘要： A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.
摘要翻译：一种可变电阻存储器件及其形成方法。该方法可以包括在衬底上形成下电极，在衬底上堆叠第一蚀刻停止层和第二蚀刻停止层，在第二蚀刻停止层上形成绝缘层，形成凹陷区域以通过图案曝光下电极绝缘层和第一和第二蚀刻停止层，在凹陷区域中形成可变电阻材料层，并在可变电阻材料层上形成上电极。第一蚀刻停止层可以相对于第二蚀刻停止层具有蚀刻选择性。

5. 发明申请

US20120228574A1 VARIABLE RESISTIVE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：可变电阻记忆体装置及其制造方法
公开(公告)号：US20120228574A1
公开(公告)日：2012-09-13
申请号：US13405990
申请日：2012-02-27
申请人： SANG-SU PARK , Jaehee Oh , Jung-In Kim
发明人： SANG-SU PARK , Jaehee Oh , Jung-In Kim
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2409 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1608
摘要： A variable resistive memory device includes a substrate comprising a cell region and a peripheral region, a word line extending in a first direction formed on the substrate of the cell region, a switching element formed on the word line, a variable resistance layer formed on the word line, and at least one transistor comprising a gate stack, the gate stack formed on the substrate of the peripheral region, wherein the word line comprises a metal layer formed at a same level as the gate stack.
摘要翻译：一种可变电阻式存储器件，包括：包括单元区域和外围区域的衬底;形成在单元区域的衬底上的第一方向上延伸的字线;形成在字线上的开关元件;形成在单元区域上的可变电阻层; 字线，以及至少一个包括栅叠层的晶体管，所述栅堆叠形成在所述外围区的所述衬底上，其中所述字线包括形成在与所述栅堆叠相同级别的金属层。

6. 发明申请

US20050175693A1 Substained release formulation of protein and preparation method thereof 审中-公开
标题翻译：蛋白质的大量释放制剂及其制备方法
公开(公告)号：US20050175693A1
公开(公告)日：2005-08-11
申请号：US10512090
申请日：2003-05-09
申请人： Hee-Yong Lee , Jung-Soo Kim , Ji-Suk Lee , Jung-In Kim , Yun-Mi Seo , Chae-Jin Lim , Sung-Kyu Kim , Young-Hwan Jung , Seung-Gu Chang , Ho-Il Choi
发明人： Hee-Yong Lee , Jung-Soo Kim , Ji-Suk Lee , Jung-In Kim , Yun-Mi Seo , Chae-Jin Lim , Sung-Kyu Kim , Young-Hwan Jung , Seung-Gu Chang , Ho-Il Choi
IPC分类号： A61K9/00 , A61K9/16 , A61K38/17 , A61K9/22 , A61K31/737
CPC分类号： A61K9/1617 , A61K9/1652
摘要： The present invention relates to a sustained release formulation comprising protein as an active ingredient, and a preparation method thereof. According to the present invention, the sustained release formulation contains protein drugs that are encapsulated in biodegradable hydrophobic matrices as pharmaceutically active forms by forming complexes with sulfated polysaccharides. The sustained release formulation prepared by the present invention can be used to effectively treat a disease without frequent injections by keeping the protein concentration at a sufficiently high level for a long period when injected in vivo once.
摘要翻译：本发明涉及包含蛋白质作为活性成分的缓释制剂及其制备方法。根据本发明，持续释放制剂含有通过与硫酸化多糖形成复合物而包封在可生物降解的疏水基质中作为药物活性形式的蛋白质药物。通过本发明制备的持续释放制剂可以用于通过在体内注射一次时将蛋白质浓度保持在足够高的水平长时间来有效地治疗疾病而不经常注射。

7. 发明申请

US20130187119A1 Semiconductor Memory Devices Having Strapping Contacts 有权
标题翻译：具有捆扎触头的半导体存储器件
公开(公告)号：US20130187119A1
公开(公告)日：2013-07-25
申请号：US13630505
申请日：2012-09-28
申请人： Jung-in Kim , Jae-hee Oh , Jun-hyok Kong , Sung-ho Eun , Yong-tae Oh
发明人： Jung-in Kim , Jae-hee Oh , Jun-hyok Kong , Sung-ho Eun , Yong-tae Oh
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , G11C5/06 , G11C8/10 , G11C11/16 , G11C13/0004 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions. The active patterns contact the first interconnection lines through strapping contacts in the strapping regions.
摘要翻译：提供了具有捆扎触点的半导体存储器件，器件包括在第一方向上的相邻单元区域之间的单元区域和绑带区域。在整个单元区域和捆扎区域中沿着第一方向延伸的活动图案在与第一方向相交的第二方向上彼此间隔开。在整个单元区域和捆扎区域沿第一方向延伸的第一互连线在第二方向上彼此间隔开，同时与有源图案重叠。沿第二方向延伸的第二互连线与单元区域中的有源图案和第一互连线相交。第二互连线在第一方向上彼此间隔开。存储单元位于单元区域中的第一和第二互连线的交叉部分处。有源图案通过捆扎区域中的捆扎触头接触第一互连线。

8. 发明申请

US20110207285A1 Method Of Forming Pattern Structure And Method Of Fabricating Semiconductor Device Using The Same 有权
标题翻译：形成图案结构的方法及使用其制造半导体器件的方法
公开(公告)号：US20110207285A1
公开(公告)日：2011-08-25
申请号：US13029449
申请日：2011-02-17
申请人： Jung-In Kim , Jaehee Oh , Kiseok Suh
发明人： Jung-In Kim , Jaehee Oh , Kiseok Suh
IPC分类号： H01L21/02 , H01L21/027
CPC分类号： H01L27/24 , H01L21/31144
摘要： A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.
摘要翻译：提供一种形成图案结构的方法和使用该图案结构制造半导体器件的方法，形成图案结构的方法包括在形成在下层上的下层上形成掩模。使用掩模作为蚀刻掩模蚀刻下层，从而在下层上形成图案。模式至少定义一个开口。在开口中形成牺牲层，并且去除掩模。当去除掩模时，开口中的牺牲层被部分蚀刻。

9. 发明授权

US07541252B2 Methods of fabricating a semiconductor device including a self-aligned cell diode 有权
标题翻译：制造包括自对准单元二极管的半导体器件的方法
公开(公告)号：US07541252B2
公开(公告)日：2009-06-02
申请号：US11770764
申请日：2007-06-29
申请人： Sung-Ho Eun , Jae-Hee Oh , Jae-Hyun Park , Jung-In Kim , Seung-Pil Ko , Yong-Tae Oh
发明人： Sung-Ho Eun , Jae-Hee Oh , Jae-Hyun Park , Jung-In Kim , Seung-Pil Ko , Yong-Tae Oh
IPC分类号： H01L21/20
CPC分类号： H01L27/2463 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： A method of fabricating a semiconductor device includes forming a conductive layer on a semiconductor substrate, forming an insulating layer on the conductive layer, forming a word line and isolation trenches by patterning the insulating layer and the conductive layer, forming an isolation layer that fills the isolation trenches, forming a cell contact hole in the insulating layer such that the cell contact hole is self-aligned with the word line and exposes the word line, and forming a cell diode in the cell contact hole.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成导电层，在导电层上形成绝缘层，通过图案化绝缘层和导电层形成字线和隔离沟槽，形成填充隔离沟槽，在绝缘层中形成电池接触孔，使得电池接触孔与字线自对准并暴露字线，并在电池接触孔中形成电池二极管。

10. 发明申请

US20080280390A1 METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE HAVING SELF-ALIGNED ELECTRODE, RELATED DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME 审中-公开
标题翻译：具有自对准电极的半导体存储器件的制造方法，相关器件及其相关的电子系统
公开(公告)号：US20080280390A1
公开(公告)日：2008-11-13
申请号：US12045612
申请日：2008-03-10
申请人： Jung-In KIM , Jae-Hee OH , Jun-Hyok KONG , Jae-Hyun PARK , Kwang-Woo LEE
发明人： Jung-In KIM , Jae-Hee OH , Jun-Hyok KONG , Jae-Hyun PARK , Kwang-Woo LEE
IPC分类号： H01L47/00
CPC分类号： H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/141 , H01L45/1683
摘要： A method of fabricating a semiconductor memory device having a self-aligned electrode is provided. An interlayer insulating layer having a contact hole is formed on a substrate. A phase change pattern partially filling the contact hole is formed. A bit line which includes a bit extension self-aligned to the phase change pattern and crosses over the interlayer insulating layer is formed. The bit extension may extend in the contact hole on the phase change pattern. The bit extension contacts the phase change pattern.
摘要翻译：提供了一种制造具有自对准电极的半导体存储器件的方法。在基板上形成具有接触孔的层间绝缘层。形成部分填充接触孔的相变图案。形成了包括与相变图案自对准并与层间绝缘层交叉的位扩展的位线。钻头延伸部可以在相变图案上的接触孔中延伸。位扩展接触相变模式。

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