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    • 1. 发明授权
    • Integrated standard cell including clock lines
    • 集成标准单元格,包括时钟线
    • US5045725A
    • 1991-09-03
    • US330613
    • 1989-03-30
    • Tohru SasakiKazuyuki OmoteJun Iwamura
    • Tohru SasakiKazuyuki OmoteJun Iwamura
    • H01L21/822G06F1/10H01L21/82H01L27/02H01L27/04
    • H01L27/0207G06F1/10
    • An integrated standard cell consisting of a plurality of standard cells each having a logical area, at least one power supply line, and one ground line, which further includes two clock signal lines for supplying clock signals. These signals are formed within each standard cell and are provided outside of the power supply line and the ground line, in parallel thereto. The two clock signal lines are connected to the logical area through each shunt line which substantially extends in the vertical direction to the clock signal lines. With this construction, a quantitative prediction for the time delay of clock signals which propagate in the clock signal lines becomes easy, thereby preventing any skew of the clock signals from occurring.
    • 由多个具有逻辑区域的标准单元,至少一个电源线和一个接地线组成的集成标准单元,还包括用于提供时钟信号的两个时钟信号线。 这些信号形成在每个标准单元内,并且并联设置在电源线和接地线的外部。 两个时钟信号线通过基本上在垂直方向上延伸到时钟信号线的分路线连接到逻辑区域。 利用这种结构,在时钟信号线中传播的时钟信号的时间延迟的定量预测变得容易,从而防止发生时钟信号的任何偏斜。
    • 2. 发明授权
    • Analog to digital converter
    • 模数转换器
    • US4635037A
    • 1987-01-06
    • US414912
    • 1982-09-03
    • Jun Iwamura
    • Jun Iwamura
    • H03M1/50H03M1/00H03M1/12H03K13/02
    • H03M1/50
    • An analog to digital converter comprising a data strobe terminal to which a signal is supplied upon the start of the converting operation, a delay circuit having a transistor with controlled conduction resistance and having its gate supplied with an analog input signal, an EX-OR gate having a first input terminal connected to the data strobe terminal and a second input terminal connected to the data strobe terminal through the delay circuit, an AND gate to which the output signal of the EX-OR gate and a clock pulse are supplied, and a counter for counting the output signal of the AND gate, whereby to produce the output of the counter as a digital signal.
    • 一种模数转换器,包括在开始转换操作时向其提供信号的数据选通端子,具有受控导通电阻的晶体管并且其门提供有模拟输入信号的延迟电路,EX-OR门 具有连接到数据选通端子的第一输入端子和通过延迟电路连接到数据选通端子的第二输入端子,提供EX-或门输出信号和时钟脉冲的与门,以及 计数器,用于对与门的输出信号进行计数,从而产生计数器的输出作为数字信号。
    • 3. 发明授权
    • Three-output level logic circuit
    • 三输出电平逻辑电路
    • US4491749A
    • 1985-01-01
    • US477897
    • 1983-03-23
    • Jun Iwamura
    • Jun Iwamura
    • H03K19/0175H03K19/094H03K19/082
    • H03K19/09425H03K19/09429
    • A three-output level logic circuit comprises an output stage and a drive stage for driving the output stage. The output stage includes first and second MOS transistors connected in series between first and second power sources and a terminal is provided for producing three-state output signals. The drive stage includes third to sixth MOS transistors connected in series between the first and second power sources. A terminal is provided for supplying a data signal to the fourth and fifth MOS transistors. A control signal is supplied in common to the gate electrodes of the third to sixth MOS transistors. The conductivity types of the first to sixth MOS transistors are selected to operate the logic circuit with one control signal input and one data signal input.
    • 三输出电平逻辑电路包括用于驱动输出级的输出级和驱动级。 输出级包括在第一和第二电源之间串联连接的第一和第二MOS晶体管,并且提供用于产生三态输出信号的端子。 驱动级包括串联连接在第一和第二电源之间的第三至第六MOS晶体管。 提供一个用于向第四和第五MOS晶体管提供数据信号的端子。 控制信号被共同地提供给第三至第六MOS晶体管的栅电极。 选择第一至第六MOS晶体管的导电类型来操作具有一个控制信号输入和一个数据信号输入的逻辑电路。