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1. 发明授权

US06596581B2 Method for manufacturing a semiconductor device having a metal-insulator-metal capacitor and a damascene wiring layer structure 失效
标题翻译：具有金属 - 绝缘体 - 金属电容器和镶嵌布线层结构的半导体器件的制造方法
公开(公告)号：US06596581B2
公开(公告)日：2003-07-22
申请号：US10196412
申请日：2002-07-17
申请人： Byung-lyul Park , Ju-hyuk Chung , Ja-hyung Han
发明人： Byung-lyul Park , Ju-hyuk Chung , Ja-hyung Han
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L21/76807 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor and a damascene wiring layer structure, wherein first and second metal wiring layers are formed in a lower dielectric layer on a semiconductor substrate such that top surfaces of the first and second metal wiring layers and the lower dielectric layer are level. First and second dielectric layers are sequentially formed to have a hole exposing the top surface of the second metal wiring layer. An upper electrode of a capacitor is formed in the hole region such that the top surfaces of the upper electrode and the second dielectric layer are level. Third and fourth dielectric layers are sequentially formed on the substrate. A damascene structure is formed to contact the top surface of the first metal wiring layer, and a contact plug is formed to contact the top surface of the upper electrode.
摘要翻译：一种制造具有金属绝缘体金属（MIM）电容器和镶嵌布线层结构的半导体器件的方法，其中第一和第二金属布线层形成在半导体衬底上的下介电层中，使得第一并且第二金属布线层和下介电层是平坦的。依次形成第一和第二电介质层，以使第二金属布线层的顶表面露出孔。在孔区域中形成电容器的上电极，使得上电极和第二电介质层的顶表面平坦。第三和第四电介质层依次形成在衬底上。形成镶嵌结构以接触第一金属布线层的顶表面，并且形成接触塞以接触上电极的顶表面。

2. 发明授权

US06849536B2 Inter-metal dielectric patterns and method of forming the same 失效
标题翻译：金属间电介质图案及其形成方法
公开(公告)号：US06849536B2
公开(公告)日：2005-02-01
申请号：US10404210
申请日：2003-04-01
申请人： Soo-Geun Lee , Ju-Hyuk Chung , Il-Goo Kim , Kyoung-Woo Lee , Wan-Jae Park , Jae-Hak Kim
发明人： Soo-Geun Lee , Ju-Hyuk Chung , Il-Goo Kim , Kyoung-Woo Lee , Wan-Jae Park , Jae-Hak Kim
IPC分类号： H01L21/28 , H01L21/316 , H01L21/768 , H01L21/4762
CPC分类号： H01L21/76831 , H01L21/316 , H01L21/31612 , H01L21/31629 , H01L21/31633 , H01L21/31695 , H01L21/76808 , H01L21/76835 , H01L2221/1036
摘要： Provided are an inter-metal dielectric pattern and a method of forming the same. The pattern includes a lower interconnection disposed on a semiconductor substrate, a lower dielectric layer having a via hole exposing the lower interconnection and covering the semiconductor substrate where the lower interconnection is disposed, and an upper dielectric pattern and a lower capping pattern, which include a trench line exposing the via hole and sequentially stacked on the lower dielectric layer. The lower dielectric layer and the upper dielectric pattern are low k-dielectric layers formed of materials such as SiO2, SiOF, SiOC, and porous dielectric. The method includes forming an inter-metal dielectric layer including a lower dielectric layer and upper dielectric layer, which are sequentially stacked, on a lower interconnection formed on a semiconductor substrate. The inter-metal dielectric layer is patterned to form a via hole, which exposes the upper side of the lower interconnection. Then, an upper capping layer is formed on the entire surface of the semiconductor substrate including the via hole. The upper capping layer and the upper dielectric layer are successively patterned to form a trench line exposing the upper side of the via hole. The upper capping layer is formed of at least one material selected from the group consisting of a silicon oxide layer, a silicon carbide layer, a silicon nitride layer, and a silicon oxynitride layer, by using PECVD.
摘要翻译：提供了金属间介电图案及其形成方法。该图案包括布置在半导体衬底上的下部互连，具有通孔暴露下部互连并覆盖半导体衬底的下部电介质图案和下部封盖图案的下部电介质层，沟槽线暴露通孔并依次堆叠在下介电层上。下电介质层和上电介质图案是由诸如SiO 2，SiOF，SiOC和多孔电介质的材料形成的低K电介质层。该方法包括在形成在半导体衬底上的下互连件上依次层叠包括下电介质层和上电介质层的金属间电介质层。图案化金属间电介质层以形成通孔，其暴露下部互连的上侧。然后，在包括通孔的半导体衬底的整个表面上形成上覆盖层。上覆盖层和上电介质层被连续地图案化以形成暴露通孔上侧的沟槽线。通过使用PECVD，上覆盖层由选自氧化硅层，碳化硅层，氮化硅层和氮氧化硅层的至少一种材料形成。

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