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1. 发明授权

US07639801B2 Method of transforming serial scrambler to parallel scrambler, parallel scrambler and double-edge-triggered register with XOR operation 有权
标题翻译：将串行扰码器转换为并行扰频器，并行加扰器和双边沿触发寄存器的异或运算方法
公开(公告)号：US07639801B2
公开(公告)日：2009-12-29
申请号：US11096957
申请日：2005-03-31
申请人： Shyh-Jye Jou , Chih-Ning Chen , You-Jiun Wang , Ju-Yuan Hsiao , Chih-Hsien Lin
发明人： Shyh-Jye Jou , Chih-Ning Chen , You-Jiun Wang , Ju-Yuan Hsiao , Chih-Hsien Lin
IPC分类号： H04L9/00
CPC分类号： H03K3/356156 , H04B2201/70707
摘要： A method of transforming a serial scrambler to a parallel scrambler, a parallel scrambler and a double-edge-triggered register with XOR operation are provided. The method transforms a serial scrambler to a parallel scrambler according to a characteristic polynomial: P ⁡ ( x ) = ∑ q = 0 N ⁢ c q ⁢ x q ⁢ ⁢ or ⁢ ⁢ b ⁡ ( i ) = ∑ q = 1 N ⁢ c q ⁢ b ⁡ ( i - q ) . The method first determines a transformation formula: b ⁡ ( kN + i ) = ∑ q = 1 N ⁢ c q ⁢ b ⁡ ( ( k - R ) ⁢ N + i + R ⁡ ( N - q ) ) according to the parameters of the characteristic polynomial. The parallel bits Bj=[bMj, bMj+1, . . . , bMj+M−2, bMj+M−1] are arranged in order. The transformation number R=2t (the initial number of t is 0) is set. The parallel bits are replaced by the transformation formula. When (k−R)N+i+R(N−q) is larger than Mj−1 in the transformation formula, 1 is added to t in the transformation formula R=2t and the transformation formula is re-counted. Finally, the XOR gates are connected to the registers according to a computed result from the transformation formula.
摘要翻译：提供了一种将串行加扰器变换为并行扰频器，并行扰频器和具有异或运算的双边沿触发寄存器的方法。该方法根据特征多项式将串扰扰码器转换为并行扰频器：P⁡（x）=Σq = 0 N cq xq ud或⁢b⁡（i）=Σq = 1 N cq b⁡（i-q）。该方法首先根据下列参数确定变换公式：b⁡（kN + i）=Σq = 1 N cq b⁡（（k-R）N + i + R⁡（N-q）特征多项式。并行位Bj = [bMj，bMj + 1，... 。。，bMj + M-2，bMj + M-1]。转换数R = 2t（t的初始数为0）被设置。并行位由变换公式代替。当变换式中（k-R）N + i + R（N-q）大于Mj-1时，在转化公式R = 2t中加入1，转化公式重新计算。最后，XOR门根据转换公式的计算结果连接到寄存器。

2. 发明申请

US20120091816A1 POWER SYSTEMS WITH MULTIPLE POWER SOURCES 审中-公开
标题翻译：具有多个电源的电力系统
公开(公告)号：US20120091816A1
公开(公告)日：2012-04-19
申请号：US13289364
申请日：2011-11-04
申请人： Da LIU , Sheng-Tai LEE , Ju-Yuan HSIAO , Chang-Yi LIN
发明人： Da LIU , Sheng-Tai LEE , Ju-Yuan HSIAO , Chang-Yi LIN
IPC分类号： H02J7/00
CPC分类号： H02J7/022 , H02J7/0068 , H02M3/158 , H05B33/0809 , Y10T307/696
摘要： In one embodiment, a power system includes a first power source having a first voltage, a second power source having a second voltage, and a controller. The controller is coupled to the first power source and the second power source. The controller compares the first voltage with the second voltage, controls the first power source to charge the second power source via a first switch and a second switch in a charging mode when the first voltage is greater than said second voltage, and controls the second power source to power a load such as a light-emitting diode (LED) light source via the second switch and a third switch in a load-powering mode when the second voltage is greater than the first voltage.
摘要翻译：在一个实施例中，电力系统包括具有第一电压的第一电源，具有第二电压的第二电源和控制器。控制器耦合到第一电源和第二电源。控制器将第一电压与第二电压进行比较，当第一电压大于所述第二电压时，控制第一电源经由第一开关和第二开关以充电模式对第二电源充电，并且控制第二电源源极，当第二电压大于第一电压时，经由第二开关和负载供电模式中的第三开关对诸如发光二极管（LED）光源的负载供电。

3. 发明申请

US20060029225A1 Method of transforming serial scrambler to parallel scrambler, parallel scrambler and double-edge-triggered register with XOR operation 有权
公开(公告)号：US20060029225A1
公开(公告)日：2006-02-09
申请号：US11096957
申请日：2005-03-31
申请人： Shyh-Jye Jou , Chih-Ning Chen , You-Jiun Wang , Ju-Yuan Hsiao , Chih-Hsien Lin
发明人： Shyh-Jye Jou , Chih-Ning Chen , You-Jiun Wang , Ju-Yuan Hsiao , Chih-Hsien Lin
IPC分类号： H04K1/06
CPC分类号： H03K3/356156 , H04B2201/70707
摘要： A method of transforming a serial scrambler to a parallel scrambler, a parallel scrambler and a double-edge-triggered register with XOR operation are provided. The method transforms a serial scrambler to a parallel scrambler according to a characteristic polynomial: P ⁡ ( x ) = ∑ q = 0 N ⁢ c q ⁢ x q ⁢ ⁢ or ⁢ ⁢ b ⁡ ( i ) = ∑ q = 1 N ⁢ c q ⁢ b ⁡ ( i - q ) . The method first determines a transformation formula: b ⁡ ( kN + i ) = ∑ q = 1 N ⁢ c q ⁢ b ⁡ ( ( k - R ) ⁢ N + i + R ⁡ ( N - q ) ) according to the parameters of the characteristic polynomial. The parallel bits Bj=[bMj, bMj+1, . . . , bMj+M−2, bMj+M−1] are arranged in order. The transformation number R=2t (the initial number of t is 0) is set. The parallel bits are replaced by the transformation formula. When (k−R)N+i+R(N−q) is larger than Mj−1 in the transformation formula, 1 is added to t in the transformation formula R=2t and the transformation formula is re-counted. Finally, the XOR gates are connected to the registers according to a computed result from the transformation formula.

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