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1. 发明授权

US08611486B2 Adjustment of clock signals regenerated from a data stream 有权
标题翻译：调整从数据流重新生成的时钟信号
公开(公告)号：US08611486B2
公开(公告)日：2013-12-17
申请号：US13083399
申请日：2011-04-08
申请人： Hoon Choi , Daekyeung Kim , Ju Hwan Yi , Young Don Bae
发明人： Hoon Choi , Daekyeung Kim , Ju Hwan Yi , Young Don Bae
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , G09G5/008 , G09G2370/10
摘要： Embodiments of the invention are generally directed to adjustment of clock signals regenerated from a data stream. An embodiment of a method includes receiving a data stream from a transmitting device via a communication link, the data stream including stream data, a link clock signal, and timestamps to indicate a relationship between the link clock signal and a stream clock signal. The method further includes adjusting the stream clock based at least in part on one or more measurements related to the data stream, the one or more measurements including a count of a number of pulses of the stream clock during a period of time, or a measurement of a number of data elements from the data stream stored in a buffer at a certain point in time.
摘要翻译：本发明的实施例一般涉及从数据流再生的时钟信号的调整。方法的实施例包括经由通信链路从发送设备接收数据流，数据流包括流数据，链路时钟信号和时间戳，以指示链路时钟信号和流时钟信号之间的关系。该方法还包括至少部分地基于与数据流相关的一个或多个测量来调整流时钟，所述一个或多个测量包括在一段时间内的流时钟的脉冲数的计数，或测量从存储在缓冲器中的某个时间点的数据流中的多个数据元素。

2. 发明授权

US08588281B2 Transceiver having embedded clock interface and method of operating transceiver 有权
标题翻译：收发器具有嵌入式时钟接口和操作收发器的方法
公开(公告)号：US08588281B2
公开(公告)日：2013-11-19
申请号：US13021883
申请日：2011-02-07
申请人： Woon-taek Oh , Jae-youl Lee , Jin-ho Kim , Tae-jin Kim , Ju-hwan Yi , Jong-shin Shin
发明人： Woon-taek Oh , Jae-youl Lee , Jin-ho Kim , Tae-jin Kim , Ju-hwan Yi , Jong-shin Shin
IPC分类号： H04B1/38
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C2207/107 , H03M9/00
摘要： A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial data into the plurality of data components in response to a second clock signal generated from the serial data. The transmitter adds at least one dummy bit to the serial data at predetermined intervals. The at least one dummy bit includes information regarding a data type of the plurality of data components.
摘要翻译：收发器包括响应于第一时钟信号将多个数据分量转换成串行数据并发送串行数据的发送器，以及接收串行数据并将串行数据转换成多个数据分量的响应于从串行数据生成的第二个时钟信号。发射机以预定间隔向串行数据添加至少一个虚拟位。至少一个虚拟位包括关于多个数据分量的数据类型的信息。

3. 发明申请

US20120147271A1 MULTIMEDIA I/O SYSTEM ARCHITECTURE FOR ADVANCED DIGITAL TELEVISION 有权
标题翻译：用于高级数字电视的多媒体I / O系统架构
公开(公告)号：US20120147271A1
公开(公告)日：2012-06-14
申请号：US13302452
申请日：2011-11-22
申请人： Hoon Choi , Daekyeung Kim , Ju Hwan Yi , Wooseung Yang , Young Il Kim , Alex Chervet , Timothy Vehling
发明人： Hoon Choi , Daekyeung Kim , Ju Hwan Yi , Wooseung Yang , Young Il Kim , Alex Chervet , Timothy Vehling
IPC分类号： H03M1/12 , H04N5/222
CPC分类号： H04N21/42607 , H04N5/765 , H04N21/4316 , H04N21/4347 , H04N21/43632 , H04N21/43635
摘要： Embodiments of the invention are generally directed to a multimedia I/O system architecture for advanced digital television. An embodiment of a multimedia system includes an I/O (input/output) control chip, the I/O control chip including one or more audio/video sub-processing engines for the processing of one or more data streams; a processing core chip for the processing of data, including audio/video data received from the I/O control chip; and one or more shared I/O channels for the transfer of data between the I/O control chip and the processing core chip.
摘要翻译：本发明的实施例通常涉及用于高级数字电视的多媒体I / O系统架构。多媒体系统的实施例包括I / O（输入/输出）控制芯片，所述I / O控制芯片包括用于处理一个或多个数据流的一个或多个音频/视频子处理引擎; 用于处理数据的处理核心芯片，包括从I / O控制芯片接收的音频/视频数据; 以及用于在I / O控制芯片和处理核心芯片之间传送数据的一个或多个共享I / O通道。

4. 发明授权

US09516372B2 Multimedia I/O system architecture for advanced digital television 有权
标题翻译：高级数字电视多媒体I / O系统架构
公开(公告)号：US09516372B2
公开(公告)日：2016-12-06
申请号：US13302452
申请日：2011-11-22
申请人： Hoon Choi , Daekyeung Kim , Ju Hwan Yi , Wooseung Yang , Young Il Kim , Alex Chervet , Timothy Vehling
发明人： Hoon Choi , Daekyeung Kim , Ju Hwan Yi , Wooseung Yang , Young Il Kim , Alex Chervet , Timothy Vehling
IPC分类号： G06F13/36 , H04N21/426 , H04N5/765 , H04N21/4363 , H04N21/431 , H04N21/434
CPC分类号： H04N21/42607 , H04N5/765 , H04N21/4316 , H04N21/4347 , H04N21/43632 , H04N21/43635
摘要： Embodiments of the invention are generally directed to a multimedia I/O system architecture for advanced digital television. An embodiment of a multimedia system includes an I/O (input/output) control chip, the I/O control chip including one or more audio/video sub-processing engines for the processing of one or more data streams; a processing core chip for the processing of data, including audio/video data received from the I/O control chip; and one or more shared I/O channels for the transfer of data between the I/O control chip and the processing core chip.
摘要翻译：本发明的实施例通常涉及用于高级数字电视的多媒体I / O系统架构。多媒体系统的实施例包括I / O（输入/输出）控制芯片，所述I / O控制芯片包括用于处理一个或多个数据流的一个或多个音频/视频子处理引擎; 用于处理数据的处理核心芯片，包括从I / O控制芯片接收的音频/视频数据; 以及用于在I / O控制芯片和处理核心芯片之间传送数据的一个或多个共享I / O通道。

5. 发明申请

US20110194590A1 TRANSCEIVER HAVING EMBEDDED CLOCK INTERFACE AND METHOD OF OPERATING TRANSCEIVER 有权
标题翻译：具有嵌入式时钟接口的收发器和操作收发器的方法
公开(公告)号：US20110194590A1
公开(公告)日：2011-08-11
申请号：US13021883
申请日：2011-02-07
申请人： Woon-taek OH , Jae-youl LEE , Jin-ho KIM , Tae-jin KIM , Ju-hwan YI , Jong-shin SHIN
发明人： Woon-taek OH , Jae-youl LEE , Jin-ho KIM , Tae-jin KIM , Ju-hwan YI , Jong-shin SHIN
IPC分类号： H04B1/38
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C2207/107 , H03M9/00
摘要： A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial data into the plurality of data components in response to a second clock signal generated from the serial data. The transmitter adds at least one dummy bit to the serial data at predetermined intervals. The at least one dummy bit includes information regarding a data type of the plurality of data components.
摘要翻译：收发器包括响应于第一时钟信号将多个数据分量转换为串行数据并发送串行数据的发送器，以及接收串行数据并将串行数据转换成多个数据分量的响应于从串行数据生成的第二个时钟信号。发射机以预定间隔向串行数据添加至少一个虚拟位。至少一个虚拟位包括关于多个数据分量的数据类型的信息。

6. 发明申请

US20090304389A1 Semiconductor apparatuses having optical connections between memory controller and memory module 有权
标题翻译：具有存储控制器和存储器模块之间的光学连接的半导体装置
公开(公告)号：US20090304389A1
公开(公告)日：2009-12-10
申请号：US12457269
申请日：2009-06-05
申请人： In-sung Joe , Kyoung-ho Ha , Ju-hwan Yi , Yoon-dong Park
发明人： In-sung Joe , Kyoung-ho Ha , Ju-hwan Yi , Yoon-dong Park
IPC分类号： H04B10/00
CPC分类号： H04B10/801 , G02B6/3885 , G02B6/42 , G02B6/4214 , G02B6/43
摘要： Semiconductor apparatuses having optical connections between a memory controller and a memory module are provided. A semiconductor apparatus includes a memory controller, at least one socket configured to receive a memory module, and a first optical-electrical module. A second optical-electrical module is mounted in the socket and optically coupled to the first optical-electrical module via at least one optical channel.
摘要翻译：提供具有存储器控制器和存储器模块之间的光学连接的半导体装置。半导体装置包括存储器控制器，配置成接收存储器模块的至少一个插座和第一光电模块。第二光电模块安装在插座中并通过至少一个光通道光耦合到第一光电模块。

7. 发明申请

US20120257699A1 ADJUSTMENT OF CLOCK SIGNALS REGENERATED FROM A DATA STREAM 有权
标题翻译：从数据流重新调整的时钟信号的调整
公开(公告)号：US20120257699A1
公开(公告)日：2012-10-11
申请号：US13083399
申请日：2011-04-08
申请人： Hoon Choi , Daekyeung Kim , Ju Hwan Yi , Young Don Bae
发明人： Hoon Choi , Daekyeung Kim , Ju Hwan Yi , Young Don Bae
IPC分类号： H04L7/02
CPC分类号： H04L7/0008 , G09G5/008 , G09G2370/10
摘要： Embodiments of the invention are generally directed to adjustment of clock signals regenerated from a data stream. An embodiment of a method includes receiving a data stream from a transmitting device via a communication link, the data stream including stream data, a link clock signal, and timestamps to indicate a relationship between the link clock signal and a stream clock signal. The method further includes adjusting the stream clock based at least in part on one or more measurements related to the data stream, the one or more measurements including a count of a number of pulses of the stream clock during a period of time, or a measurement of a number of data elements from the data stream stored in a buffer at a certain point in time.
摘要翻译：本发明的实施例一般涉及从数据流再生的时钟信号的调整。方法的实施例包括经由通信链路从发送设备接收数据流，数据流包括流数据，链路时钟信号和时间戳，以指示链路时钟信号和流时钟信号之间的关系。该方法还包括至少部分地基于与数据流相关的一个或多个测量来调整流时钟，所述一个或多个测量包括在一段时间内的流时钟的脉冲数的计数，或测量从存储在缓冲器中的某个时间点的数据流中的多个数据元素。

8. 发明申请

US20100327910A1 Interface device and interface system 失效
标题翻译：接口设备和接口系统
公开(公告)号：US20100327910A1
公开(公告)日：2010-12-30
申请号：US12662246
申请日：2010-04-07
申请人： Ju-Hwan Yi
发明人： Ju-Hwan Yi
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509 , H04L25/0272
摘要： An interface device includes a differential signal transmitter, a differential signal receiver, a first coupling capacitor, a second coupling capacitor, a direct current (DC) signal transmitter, and a DC signal receiver. The differential signal transmitter transmits a differential signal to the differential signal receiver via a differential signal line including a first signal line and a second signal line. The first coupling capacitor is communicatively coupled to the first signal line and to the differential signal transmitter. The second coupling capacitor is communicatively coupled to the first signal line and to the differential signal receiver. The DC signal transmitter transmits a DC signal via the first signal line. The DC signal receiver receives the DC signal via the first signal line.
摘要翻译：接口装置包括差分信号发射器，差分信号接收器，第一耦合电容器，第二耦合电容器，直流（DC）信号发射器和直流信号接收器。差分信号发送器经由包括第一信号线和第二信号线的差分信号线将差分信号发送到差分信号接收器。第一耦合电容器通信地耦合到第一信号线和差分信号发射器。第二耦合电容器通信地耦合到第一信号线和差分信号接收器。 DC信号发送器经由第一信号线发送DC信号。直流信号接收器经由第一信号线接收直流信号。

9. 发明授权

US08275085B2 Apparatus and method for recovering data 失效
标题翻译：用于恢复数据的装置和方法
公开(公告)号：US08275085B2
公开(公告)日：2012-09-25
申请号：US12052091
申请日：2008-03-20
申请人： Ju-hwan Yi
发明人： Ju-hwan Yi
IPC分类号： H04L7/02
CPC分类号： H04L7/0331 , H04L1/0003 , H04L1/1867 , H04L7/0029 , H04L7/0334
摘要： An apparatus for recovering data and a method thereof are provided. The apparatus includes a reference clock generator which generates a reference clock, and a data recovering unit which detects an edge of received data and recovers the data using a time difference between a reference point of the reference clock and the detected edge.
摘要翻译：提供了一种用于恢复数据的装置及其方法。该装置包括产生参考时钟的参考时钟发生器和检测接收数据的边沿并使用参考时钟的参考点与检测到的边沿之间的时间差来恢复数据的数据恢复单元。

10. 发明申请

US20090135975A1 APPARATUS AND METHOD FOR RECOVERING DATA 失效
标题翻译：用于恢复数据的装置和方法
公开(公告)号：US20090135975A1
公开(公告)日：2009-05-28
申请号：US12052091
申请日：2008-03-20
申请人： Ju-hwan Yi
发明人： Ju-hwan Yi
IPC分类号： H04L7/02
CPC分类号： H04L7/0331 , H04L1/0003 , H04L1/1867 , H04L7/0029 , H04L7/0334
摘要： An apparatus for recovering data and a method thereof are provided. The apparatus includes a reference clock generator which generates a reference clock, and a data recovering unit which detects an edge of received data and recovers the data using a time difference between a reference point of the reference clock and the detected edge.
摘要翻译：提供了一种用于恢复数据的装置及其方法。该装置包括产生参考时钟的参考时钟发生器和检测接收数据的边沿并使用参考时钟的参考点与检测到的边沿之间的时间差来恢复数据的数据恢复单元。

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