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    • 1. 发明授权
    • Motor drive circuit
    • 电机驱动电路
    • US06275405B1
    • 2001-08-14
    • US09458217
    • 1999-12-09
    • Joseph Pernyeszi
    • Joseph Pernyeszi
    • H02M506
    • H02M5/14H02P27/024
    • A phase converter for converting single-phase power to three-phase power, wherein the single-phase power is provided at a first and a second single-phase power terminal and the three-phase power is provided to a first, a second and a third three-phase power terminal, the phase converter comprising: a first power transfer means for coupling the first single-phase power terminal to the first three-phase power terminal; a second power transfer means for coupling the second single-phase power terminal to the second three-phase power terminal; and an inverter coupled to receive power from the first and second single-phase power terminals. The inverter provides power to the third three-phase power terminal and a neutral output by phase shifting its input power by ninety degrees.
    • 一种用于将单相电力转换为三相电力的相位转换器,其中单相电力被提供在第一和第二单相电源端子处,并且三相电力被提供给第一,第二和第二相 第三三相电源端子,所述相位转换器包括:用于将所述第一单相电源端子耦合到所述第一三相电力端子的第一电力传送装置; 用于将第二单相电源端子耦合到第二三相电源端子的第二电力传送装置; 以及耦合以从第一和第二单相电源端子接收电力的逆变器。 逆变器通过将其输入功率相移90度来向第三个三相电源端子和中性点输出提供电源。
    • 4. 发明申请
    • Monolithic DMOS Transistor in Junction Isolated Process
    • 单片DMOS晶体管在隔离工艺中的应用
    • US20160163791A1
    • 2016-06-09
    • US14959286
    • 2015-12-04
    • Joseph Pernyeszi
    • Joseph Pernyeszi
    • H01L29/06H01L29/10H01L29/78
    • H01L29/0634H01L21/76237H01L29/0692H01L29/0886H01L29/1095H01L29/7816
    • A high voltage DMOS half-bridge output for various DC to DC converters on a monolithic, junction isolated wafer is presented. A high-side lateral DMOS transistor is based on the epi extension diffusion and a five layer RESURF structure. The five layers are made possible by the epi extension diffusion which is formed by a suitable n-type dopant diffused into a p-type substrate and it is the same polarity as the epi. The five layers, starting with the p-type substrate, are the substrate, the n-type epi extension diffusion, a p-type buried layer, the n-type epi and a shallow p-type layer at the top of the epi. The epi extension is also used to shape the electric field by a specific lateral distribution and make the lateral and vertical electric fields to be the smoothest to avoid electric field induced breakdown in the silicon or oxide layers above the silicon.
    • 提出了一种用于单片,隔离晶圆上的各种DC-DC转换器的高压DMOS半桥输出。 高侧横向DMOS晶体管基于外延扩展扩散和五层RESURF结构。 通过由扩散到p型衬底中的合适的n型掺杂物形成的外延延伸扩散使得五层成为可能,并且它与epi具有相同的极性。 从p型衬底开始的五层是epi顶部的衬底,n型epi延伸扩散,p型掩埋层,n型epi和浅p型层。 外延扩展还用于通过特定的横向分布来形成电场,并且使得横向和垂直电场是最平滑的,以避免在硅上方的硅或氧化物层中的电场引起的击穿。
    • 6. 发明授权
    • MOSFET Logic inverter buffer circuit for integrated circuits
    • 用于集成电路的Mosfet逻辑逆变缓冲电路
    • US4395645A
    • 1983-07-26
    • US213533
    • 1980-12-05
    • Joseph Pernyeszi
    • Joseph Pernyeszi
    • H03K19/0175H03K19/0185H03K19/0944H03K19/094H03K3/353H03K17/687H03K19/20
    • H03K19/018507H03K19/09445H03K19/09446
    • The inverter buffer circuit disclosed includes two transistorized circuits each coupled to an input circuit and an output circuit capable of carrying high current and providing full output swing between a high voltage or binary "1" and a low voltage or binary "0". Each of the two circuits include a first enhancement field effect transistor having its drain electrode connected to a drain voltage and operating as a source follower, a first depletion field effect transistor having its drain electrode and source electrode connected to back bias acting as a load for the first enhancement transistor, second and third enhancement field effect transistors having their source electrodes coupled to the back bias and interconnected to form a flip-flop controlled by the first enhancement transistor and a second depletion field effect transistor having its drain electrode coupled to the drain voltage and acting as the load for the flip-flop. The output circuit includes two depletion field effect transistors connected in series between the drain voltage and source voltage with the gate electrodes thereof connected to a different one of the two flip-flops and an output terminal coupled to the series connection between the two depletion transistors. Three embodiments of the input circuit are disclosed.
    • 所公开的逆变器缓冲电路包括两个晶体管电路,每个都耦合到输入电路和能够承载高电流并在高电压或二进制“1”与低电压或二进制“0”之间提供全输出摆幅的输出电路。 两个电路中的每一个包括第一增强场效应晶体管,其第一增强场效应晶体管的漏极连接到漏极电压并用作源极跟随器,第一耗尽场效应晶体管的漏极电极和源电极连接到反偏压,用作负载 第一增强型晶体管,第二和第三增强场效应晶体管的源极耦合到背偏置并互连,以形成由第一增强晶体管控制的触发器和第二耗尽场效应晶体管,其漏极连接到漏极 并作为触发器的负载。 输出电路包括串联连接在漏极电压和源极电压之间的两个耗尽场效应晶体管,其栅电极连接到两个触发器中的不同一个,以及耦合到两个耗尽晶体管之间的串联连接的输出端子。 公开了输入电路的三个实施例。
    • 7. 发明授权
    • Power source with an electronic impedance changer
    • 电源带有电子阻抗变换器
    • US4333133A
    • 1982-06-01
    • US189470
    • 1980-09-22
    • Joseph Pernyeszi
    • Joseph Pernyeszi
    • H02M3/156H02M3/00H02P13/18
    • H02M3/156
    • A circuit arrangement to provide a fixed voltage source in series with an arbitrarily chosen impedance of any magnitude and phase shift having very low power dissipation and capable of being fabricated on silicon integrated chips is disclosed. The circuit arrangement includes a sensing resistor to sense the output current of a power converter which is amplified and fed back with an appropriate phase shift to control the output voltage of the converter. An independent control signal may be combined with the fed back voltage to change the chosen impedance to another type of impedance.
    • 公开了一种提供固定电压源的电路装置,其具有任意幅度和相移的任意选择的阻抗,该阻抗具有非常低的功率消耗并能够制造在硅集成芯片上。 电路装置包括用于检测功率转换器的输出电流的感测电阻器,其被放大并用适当的相移反馈以控制转换器的输出电压。 独立的控制信号可以与反馈电压组合以将所选择的阻抗改变成另一种类型的阻抗。
    • 8. 发明授权
    • Monolithic DMOS transistor in junction isolated process
    • 单片DMOS晶体管在隔离过程中
    • US09570547B2
    • 2017-02-14
    • US14959286
    • 2015-12-04
    • Joseph Pernyeszi
    • Joseph Pernyeszi
    • H01L29/94H01L29/06H01L29/78H01L29/08H01L29/10H01L21/762
    • H01L29/0634H01L21/76237H01L29/0692H01L29/0886H01L29/1095H01L29/7816
    • A high voltage DMOS half-bridge output for various DC to DC converters on a monolithic, junction isolated wafer is presented. A high-side lateral DMOS transistor is based on the epi extension diffusion and a five layer RESURF structure. The five layers are made possible by the epi extension diffusion which is formed by a suitable n-type dopant diffused into a p-type substrate and it is the same polarity as the epi. The five layers, starting with the p-type substrate, are the substrate, the n-type epi extension diffusion, a p-type buried layer, the n-type epi and a shallow p-type layer at the top of the epi. The epi extension is also used to shape the electric field by a specific lateral distribution and make the lateral and vertical electric fields to be the smoothest to avoid electric field induced breakdown in the silicon or oxide layers above the silicon.
    • 提出了一种用于单片,隔离晶圆上的各种DC-DC转换器的高压DMOS半桥输出。 高侧横向DMOS晶体管基于外延扩展扩散和五层RESURF结构。 通过由扩散到p型衬底中的合适的n型掺杂物形成的外延延伸扩散使得五层成为可能,并且它与epi具有相同的极性。 从p型衬底开始的五层是epi顶部的衬底,n型epi延伸扩散,p型掩埋层,n型epi和浅p型层。 外延扩展还用于通过特定的横向分布来形成电场,并且使得横向和垂直电场是最平滑的,以避免在硅上方的硅或氧化物层中的电场引起的击穿。