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1. 发明申请

US20110101787A1 SERIES/PARALLEL POWER SUPPLY SWITCHING 失效
标题翻译：系列/并联电源开关
公开(公告)号：US20110101787A1
公开(公告)日：2011-05-05
申请号：US12707103
申请日：2010-02-17
申请人： Stephen Joseph Gaul
发明人： Stephen Joseph Gaul
IPC分类号： H02J3/00
CPC分类号： H01L31/02021 , Y02E10/50 , Y10T307/653 , Y10T307/724
摘要： A device which can dynamically configure an array of power supply cells such as photovoltaic (PV) solar cells to provide power to a load device based on the power requirements of the load device. By selectively configuring the array of power supply cells according to one of a number of available series/parallel connection schemes, the supplied power can be more closely tailored by a controller to the requirements of the load device.
摘要翻译：可以动态地配置诸如光伏（PV）太阳能电池的电源单元阵列的装置，以基于负载装置的功率要求为负载装置提供电力。通过根据多个可用的串联/并联方案之一选择性地配置电源单元阵列，所提供的功率可以由控制器更加紧密地根据负载设备的要求来定制。

2. 发明授权

US07804143B2 Radiation hardened device 失效
标题翻译：辐射硬化装置
公开(公告)号：US07804143B2
公开(公告)日：2010-09-28
申请号：US12372893
申请日：2009-02-18
申请人： Stephen Joseph Gaul , Michael D. Church , Brent R. Doyle
发明人： Stephen Joseph Gaul , Michael D. Church , Brent R. Doyle
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/761 , H01L21/823481 , H01L29/1083
摘要： A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.
摘要翻译： “标签”MOS器件提供辐射硬度，同时支持减小栅极宽度要求。 “标签式”MOS器件还采用了机身连接环，可减少磁场阈值泄漏。在一个实现中，“标签式”MOS器件被设计成使得突片的宽度基于MOS器件的至少沟道长度，使得器件的源极和漏极区域之间的辐射诱导寄生传导路径具有电阻高于器件沟道电阻。

3. 发明申请

US20100191383A1 CONNECTION SYSTEMS AND METHODS FOR SOLAR CELLS 审中-公开
标题翻译：太阳能电池的连接系统和方法
公开(公告)号：US20100191383A1
公开(公告)日：2010-07-29
申请号：US12684512
申请日：2010-01-08
申请人： Stephen Joseph Gaul
发明人： Stephen Joseph Gaul
IPC分类号： H01L31/042 , G06F1/26
CPC分类号： H04L12/40013 , H01L27/142 , H01L31/02021 , H01L31/0475 , Y02E10/50
摘要： Exemplary embodiments provide an array of solar power generation devices, and method for forming the array. Each solar power generation device can be defined as a cell, a group of cells, a panel subarray, a panel from an array of panels, etc. The solar power generation device can include a controller which can address and control each solar power generation device individually. A test method and fixture is also described, which can be used to program the controller such that incorrect assembly of the array during manufacture is overcome.
摘要翻译：示例性实施例提供了太阳能发电装置的阵列，以及用于形成阵列的方法。每个太阳能发电装置可以被定义为电池，一组电池，面板子阵列，面板阵列的面板等。太阳能发电装置可以包括控制器，其可以解决和控制每个太阳能发电装置单独。还描述了测试方法和夹具，其可以用于对控制器进行编程，从而克服了制造期间阵列的错误组装。

4. 发明授权

US5825092A Integrated circuit with an air bridge having a lid 失效
标题翻译：具有盖的空气桥的集成电路
公开(公告)号：US5825092A
公开(公告)日：1998-10-20
申请号：US650688
申请日：1996-05-20
申请人： Jose Avelino Delgado , Stephen Joseph Gaul
发明人： Jose Avelino Delgado , Stephen Joseph Gaul
IPC分类号： H01L25/00 , H01L21/48 , H01L23/13 , H01L23/64 , H01L29/04 , H01L23/48 , H01L29/80
CPC分类号： H01L21/4803 , H01L23/13 , H01L23/642 , H01L23/645 , H01L2924/0002
摘要： An air bridge structure 102 is formed in a cavity of a glass lid substrate. The air bridge structure is bonded to an integrated circuit in a device substrate 82 to provide an air bridge structure coupled to the integrated circuit.
摘要翻译：空气桥结构102形成在玻璃盖基板的空腔中。空气桥结构被结合到器件基板82中的集成电路以提供耦合到集成电路的空气桥结构。

5. 发明授权

US5814889A Intergrated circuit with coaxial isolation and method 失效
标题翻译：集成电路同轴隔离和方法
公开(公告)号：US5814889A
公开(公告)日：1998-09-29
申请号：US461037
申请日：1995-06-05
申请人： Stephen Joseph Gaul
发明人： Stephen Joseph Gaul
IPC分类号： H01L21/763 , H01L23/48 , H01L27/00
CPC分类号： H01L21/763 , H01L23/481 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/16195 , H01L2924/3025
摘要： A die 810 has an outer, annular via 814 filled with conductive material in order to electrically shield an inner via 816. A die 820 can be electrically shielded from another area 822 by use of a wall 823 having a trench with oxidized side walls and a conductive filling.
摘要翻译：模具810具有填充有导电材料的外部环形通孔814，以便电屏蔽内部通孔816.裸片820可以通过使用具有带氧化侧壁的沟槽的壁823与另一区域822电隔离，并且导电填充。

6. 发明授权

US08232137B2 Heat conduction for chip stacks and 3-D circuits 失效
标题翻译：芯片堆叠和3-D电路的导热
公开(公告)号：US08232137B2
公开(公告)日：2012-07-31
申请号：US12773275
申请日：2010-05-04
申请人： Stephen Joseph Gaul , Francois Hebert
发明人： Stephen Joseph Gaul , Francois Hebert
IPC分类号： H01L21/00
CPC分类号： H01L23/3732 , H01L23/3677 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/14 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/06181 , H01L2224/06515 , H01L2224/1403 , H01L2224/14515 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/1305 , H01L2924/13062 , H01L2924/14 , H01L2924/00
摘要： A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.
摘要翻译：半导体器件组件和方法可以包括单个半导体层或层叠的半导体层，例如半导体晶片或晶片部分（半导体晶片）。在每个半导体层上，通过其形成的金刚石层可有助于散热和散热。金刚石层可以包括半导体层背面的第一部分和垂直延伸到半导体层中的一个或多个第二部分，例如完全穿过半导体层。然后可以对金刚石层进行热接触以将热量从一个或多个半导体层导出。可以通过金刚石层形成导电通孔，以提供信号路由和散热能力。

7. 发明申请

US20110115047A1 SEMICONDUCTOR PROCESS USING MASK OPENINGS OF VARYING WIDTHS TO FORM TWO OR MORE DEVICE STRUCTURES 审中-公开
标题翻译：半导体工艺使用变化的宽度来形成两个或多个器件结构
公开(公告)号：US20110115047A1
公开(公告)日：2011-05-19
申请号：US12794236
申请日：2010-06-04
申请人： Francois Hebert , Aaron Gibby , Stephen Joseph Gaul
发明人： Francois Hebert , Aaron Gibby , Stephen Joseph Gaul
IPC分类号： H01L29/06 , H01L21/02 , H01L21/331 , H01L29/73 , H01L21/306
CPC分类号： H01L21/743 , H01L21/76229 , H01L21/8222 , H01L21/8228 , H01L21/8249 , H01L27/0733 , H01L28/90 , H01L29/66272
摘要： Methods and structures for a semiconductor device can use mask openings of varying widths to form structures of different depths, different materials, and different functionality. For example, processes and structures for forming shallow trench isolation, deep isolation, trench capacitors, base, emitter, and collector, among other structures for a lateral bipolar transistor are described.
摘要翻译：半导体器件的方法和结构可以使用不同宽度的掩模开口来形成不同深度，不同材料和不同功能的结构。例如，描述了用于形成浅沟槽隔离，深隔离，沟槽电容器，基极，发射极和集电极以及横向双极晶体管的其它结构的工艺和结构。

8. 发明授权

US5773891A Integrated circuit method for and structure with narrow line widths 失效
标题翻译：集成电路方法，结构窄线宽
公开(公告)号：US5773891A
公开(公告)日：1998-06-30
申请号：US460993
申请日：1995-06-05
申请人： Jose Avelino Delgado , Stephen Joseph Gaul
发明人： Jose Avelino Delgado , Stephen Joseph Gaul
IPC分类号： H01L21/033 , H01L21/3213 , H01L21/331 , H01L21/336 , H01L21/337 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/808 , H01L29/74 , H01L29/76 , H01L29/94 , H01L31/0328
CPC分类号： H01L29/66606 , H01L21/0337 , H01L21/32139 , H01L29/1058 , H01L29/1066 , H01L29/41775 , H01L29/42376 , H01L29/66272 , H01L29/66901 , H01L29/7833 , H01L29/808 , Y10S438/981
摘要： In a sub-micron line width process, a first layer of polysilicon 13 is patterned into lines 1,2 spaced a predetermined distance. An oxide layer 11 is deposited. A second layer of polysilicon 14 is deposited on the insulating layer. A gate contact 19 or emitter contact 35 is formed from the second polysilicon layer 14. The gate 19 or emitter 35 is spaced from the lines 1,2 a distance approximately equal to the thickness of the second polysilicon layer 14.
摘要翻译：在亚微米线宽工艺中，第一层多晶硅13被图案化成间隔预定距离的线路1,2。沉积氧化物层11。第二层多晶硅14沉积在绝缘层上。栅极接触19或发射极接触35由第二多晶硅层14形成。栅极19或发射极35与线路1,2间隔大约等于第二多晶硅层14的厚度。

9. 发明授权

US07709907B2 ESD structure 有权
标题翻译： ESD结构
公开(公告)号：US07709907B2
公开(公告)日：2010-05-04
申请号：US11267175
申请日：2005-11-07
申请人： Stephen Joseph Gaul , Michael D. Church , James Edwin Vinson
发明人： Stephen Joseph Gaul , Michael D. Church , James Edwin Vinson
IPC分类号： H01L27/088
CPC分类号： H01L29/78 , H01L27/0251
摘要： An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the formation of metal silicides into the dislocation region. The spacing of the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation region is produced by providing additional lateral opposed second gate regions or oxide barrier layer extending from the oxide layer into the adjacent regions of the substrate region and the first gate region extending therebetween. Both the first gate region and the two second gate regions or barrier layer are used in the self-aligned processing of the source and drain regions. The first gate region defines the length of the channel, while the two opposed second gate regions or barrier layer define the width of the channel region. The second gate portion or barrier extends sufficiently into the substrate region to space the width of the channel from the adjacent edge of the opening in the oxide.
摘要翻译： IGFET，其通过从源极和漏极区域的相邻边缘和位错移位源极和漏极区域的侧边缘来最小化器件区域边缘处位错的影响。这使源极和漏极杂质的横向扩散和金属硅化物形成到位错区域最小化。源极和漏极区域与开口的相邻边缘和位错区域的横向边缘的间隔通过提供从氧化物层延伸到衬底区域的相邻区域中的附加横向相对的第二栅极区域或氧化物阻挡层而产生并且其间延伸的第一栅极区域。在源极和漏极区域的自对准处理中都使用第一栅极区域和两个第二栅极区域或势垒层。第一栅极区域限定沟道的长度，而两个相对的第二栅极区域或阻挡层限定沟道区域的宽度。第二栅极部分或屏障充分延伸到衬底区域中，以使通道的宽度与氧化物中的开口的相邻边缘相隔离。

10. 发明授权

US5949144A Pre-bond cavity air bridge 失效
标题翻译：预键腔空气桥
公开(公告)号：US5949144A
公开(公告)日：1999-09-07
申请号：US650762
申请日：1996-05-20
申请人： Jose Avelino Delgado , Stephen Joseph Gaul
发明人： Jose Avelino Delgado , Stephen Joseph Gaul
IPC分类号： H01L23/522 , H01L21/20 , H01L21/762 , H01L21/768 , H01L23/482 , H01L27/12 , H01L29/80
CPC分类号： H01L23/4821 , H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76289 , H01L2924/0002
摘要： A handle wafer has a cavity coated with a dielectric. A device wafer is bonded to the handle wafer. Metal lines, devices or circuits fabricated on device layer overlay the cavity in the handle wafer thus reducing parasitic capacitances to the handle wafer and crosstalk through the handle wafer. This constitutes a rugged air bridge structure capable of being passivated and/or being placed in plastic packages.
摘要翻译：处理晶片具有涂覆有电介质的腔体。器件晶片被结合到处理晶片。在器件层上制造的金属线，器件或电路覆盖在处理晶片中的空腔，从而降低了对晶片的寄生电容和通过处理晶片的串扰。这构成了能够被钝化和/或放置在塑料包装中的坚固的空气桥结构。

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