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1. 发明授权

US07642943B1 Analog-to-digital converter circuit and method with programmable resolution 失效
标题翻译：模数转换电路和可编程分辨率的方法
公开(公告)号：US07642943B1
公开(公告)日：2010-01-05
申请号：US11963314
申请日：2007-12-21
申请人： Joseph Cetin , Jason Muriby , Matthew Sienko , Ibrahim Yayla
发明人： Joseph Cetin , Jason Muriby , Matthew Sienko , Ibrahim Yayla
IPC分类号： H03M1/12
CPC分类号： H03M1/007 , H03M1/162 , H03M1/20
摘要： Disclosed are a circuit and a method for an analog-to-digital conversion with programmable resolution. The circuit includes a resistor ladder comprising a plurality of resistors coupled to a plurality of comparators; wherein the resistor ladder is further coupled to a switch logic circuit and a plurality of current sources; and wherein the switch logic circuit is configured to control an operation of a plurality of switches to alter conversion resolution of the ADC, and an error correction circuit coupled to the outputs of the plurality of comparators, wherein the ADC is configured to perform a first conversion step and a second conversion step, and wherein the ADC is configured to perform only the first conversion step when programmed for lower conversion accuracy and higher conversion speed.
摘要翻译：公开了一种具有可编程分辨率的模数转换的电路和方法。该电路包括一个电阻梯，包括耦合到多个比较器的多个电阻器; 其中所述电阻梯还进一步耦合到开关逻辑电路和多个电流源; 并且其中所述开关逻辑电路被配置为控制多个开关的操作以改变所述ADC的转换分辨率，以及耦合到所述多个比较器的输出的纠错电路，其中所述ADC被配置为执行第一转换步骤和第二转换步骤，并且其中所述ADC被配置为仅当编程为较低转换精度和较高转换速度时才执行第一转换步骤。

2. 发明申请

US20060071729A1 Clock circuit and method 有权
标题翻译：时钟电路和方法
公开(公告)号：US20060071729A1
公开(公告)日：2006-04-06
申请号：US11230587
申请日：2005-09-20
申请人： Joseph Cetin , Jason Muriby
发明人： Joseph Cetin , Jason Muriby
IPC分类号： H03B5/32
CPC分类号： H03B5/364 , G06F1/04 , H03B5/06 , H03B2200/0066 , H03K3/02315
摘要： A clock circuit has a crystal. A differential amplifier has a first input coupled to a first node of the crystal and a second input of the differential amplifier coupled to a bias signal and an output of the differential amplifier coupled to a second node of the crystal.
摘要翻译：时钟电路具有晶体。差分放大器具有耦合到晶体的第一节点的第一输入和耦合到偏置信号的差分放大器的第二输入和耦合到晶体的第二节点的差分放大器的输出。

3. 发明申请

US20050213268A1 Method and circuit for improving device power up timing and predictability 审中-公开
标题翻译：用于提高设备上电时间和可预测性的方法和电路
公开(公告)号：US20050213268A1
公开(公告)日：2005-09-29
申请号：US11088029
申请日：2005-03-22
申请人： Joseph Cetin , Nathan Moyal
发明人： Joseph Cetin , Nathan Moyal
IPC分类号： G05F1/56 , H02H7/00
CPC分类号： G05F1/56
摘要： Method and system for controllably and sequentially powering up subsystems of an electronic system, device or integrated circuit. In one example, a first supply voltage is selectively applied to a first subsystem, and when the first supply voltage has reached a predetermined value, a second supply voltage is selectively applied to the second subsystem. The first and second supply voltages may also be boosted to provide fast startup timing. In this manner, the first subsystem is powered-up before the second supply voltage is applied to the second subsystem—this provides for controlled, sequential power up of the subsystems of the electronic system, device or integrated circuit.
摘要翻译：用于可控地和顺序地为电子系统，设备或集成电路的子系统供电的方法和系统。在一个示例中，第一电源电压被选择性地施加到第一子系统，并且当第一电源电压已经达到预定值时，第二电源电压被选择性地施加到第二子系统。也可以提高第一和第二电源电压以提供快速的启动定时。以这种方式，在将第二电源电压施加到第二子系统之前，第一子系统被加电 - 这提供了电子系统，装置或集成电路的子系统的受控的顺序上电。

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