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1. 发明申请

US20050276131A1 Semiconductor memory device and burn-in test method therefor 审中-公开
标题翻译：半导体存储器件及其老化测试方法
公开(公告)号：US20050276131A1
公开(公告)日：2005-12-15
申请号：US11020323
申请日：2004-12-27
申请人： Woo-Jin Kim , Kwang-Joon Park , Joo-Seok Kwak , Kwang-Won Lee , Jong-Jin Yi
发明人： Woo-Jin Kim , Kwang-Joon Park , Joo-Seok Kwak , Kwang-Won Lee , Jong-Jin Yi
IPC分类号： G11C29/00 , G11C7/00 , G11C29/36
CPC分类号： G11C29/12005 , G11C29/36
摘要： A semiconductor memory device includes a switch circuit that inverts input data or output data when burn-in mode enable signals are activated or a control signal switch that inverts external control signals or internal control signals when burn-in mode enable signals are activated. A burn-in test method for the semiconductor memory device performs a pass/fail decision to determine whether the output data has passed or failed based on an inverted logical value of the input data.
摘要翻译：半导体存储器件包括一个开关电路，当老化模式使能信号被激活时，其反相输入数据或输出数据，或者当老化模式使能信号被激活时转换外部控制信号或内部控制信号的控制信号开关。半导体存储器件的老化测试方法基于输入数据的反相逻辑值执行通过/失败判定以确定输出数据是否通过或失败。

2. 发明申请

US20070127300A1 Bun-in test method semiconductor memory device 审中-公开
标题翻译： Bun-in测试方法半导体存储器件
公开(公告)号：US20070127300A1
公开(公告)日：2007-06-07
申请号：US11647398
申请日：2006-12-29
申请人： Woo-Jin Kim , Kwang-Joon Park , Joo-Seok Kwak , Kwang-Won Lee , Jong-Jin Yi
发明人： Woo-Jin Kim , Kwang-Joon Park , Joo-Seok Kwak , Kwang-Won Lee , Jong-Jin Yi
IPC分类号： G11C29/00
CPC分类号： G11C29/12005 , G11C29/36
摘要： A semiconductor memory device includes a switch circuit that inverts input data or output data when burn-in mode enable signals are activated or a control signal switch that inverts external control signals or internal control signals when burn-in mode enable signals are activated. A burn-in test method for the semiconductor memory device performs a pass/fail decision to determine whether the output data has passed or failed based on an inverted logical value of the input data.
摘要翻译：半导体存储器件包括一个开关电路，当老化模式使能信号被激活时，其反相输入数据或输出数据，或者当老化模式使能信号被激活时转换外部控制信号或内部控制信号的控制信号开关。半导体存储器件的老化测试方法基于输入数据的反相逻辑值执行通过/失败判定以确定输出数据是否通过或失败。

3. 发明申请

US20060158205A1 Method for testing standby current of semiconductor package 失效
标题翻译：半导体封装待机电流测试方法
公开(公告)号：US20060158205A1
公开(公告)日：2006-07-20
申请号：US11335270
申请日：2006-01-18
申请人： Moon-Bo Sim , Joo-Seok Kwak , Seong-Su Kim , Yun-Bo Yang , Sun-Ki Kim
发明人： Moon-Bo Sim , Joo-Seok Kwak , Seong-Su Kim , Yun-Bo Yang , Sun-Ki Kim
IPC分类号： G01R31/02
CPC分类号： G01R31/3008
摘要： A system and method for testing standby current of a semiconductor package is provided. The method includes testing semiconductor chips formed on a wafer having a predetermined wafer run number, collecting measured values of standby current of the semiconductor chips, and storing the measured values of standby current in a database, by using a wafer tester; recognizing a wafer run number of each of semiconductor packages to be tested; downloading measured values of standby current of semiconductor chips corresponding to the recognized wafer run number from the database to a semiconductor package tester; extracting a boundary value defining predetermined upper values of the downloaded measured values of standby current, by using the semiconductor package tester; setting the boundary value as a standby current limit of a program for testing the semiconductor packages by use of the semiconductor package tester; and testing the semiconductor packages based on the standby current limit.
摘要翻译：提供一种用于测试半导体封装的待机电流的系统和方法。该方法包括测试形成在具有预定晶圆行程号的晶片上的半导体芯片，收集半导体芯片的待机电流的测量值，并通过使用晶片测试器将待机电流的测量值存储在数据库中; 识别要测试的每个半导体封装的晶片运行次数; 将与识别的晶片运行数相对应的半导体芯片的待机电流的测量值从数据库下载到半导体封装测试器; 通过使用半导体封装测试器提取定义下载的待机电流测量值的预定上限值的边界值; 将边界值设置为通过使用半导体封装测试器来测试半导体封装的程序的备用电流极限; 并根据待机电流限制测试半导体封装。

4. 发明授权

US07368933B2 Method for testing standby current of semiconductor package 失效
标题翻译：半导体封装待机电流测试方法
公开(公告)号：US07368933B2
公开(公告)日：2008-05-06
申请号：US11335270
申请日：2006-01-18
申请人： Moon-Bo Sim , Joo-Seok Kwak , Seong-Su Kim , Yun-Bo Yang , Sun-Ki Kim
发明人： Moon-Bo Sim , Joo-Seok Kwak , Seong-Su Kim , Yun-Bo Yang , Sun-Ki Kim
IPC分类号： G01R31/01 , G01R31/28 , G01R31/26
CPC分类号： G01R31/3008
摘要： A system and method for testing standby current of a semiconductor package is provided. The method includes testing semiconductor chips formed on a wafer having a predetermined wafer run number, collecting measured values of standby current of the semiconductor chips, and storing the measured values of standby current in a database, by using a wafer tester; recognizing a wafer run number of each of semiconductor packages to be tested; downloading measured values of standby current of semiconductor chips corresponding to the recognized wafer run number from the database to a semiconductor package tester; extracting a boundary value defining predetermined upper values of the downloaded measured values of standby current, by using the semiconductor package tester; setting the boundary value as a standby current limit of a program for testing the semiconductor packages by use of the semiconductor package tester; and testing the semiconductor packages based on the standby current limit.
摘要翻译：提供一种用于测试半导体封装的待机电流的系统和方法。该方法包括测试形成在具有预定晶圆行程号的晶片上的半导体芯片，收集半导体芯片的待机电流的测量值，并通过使用晶片测试器将待机电流的测量值存储在数据库中; 识别要测试的每个半导体封装的晶片运行次数; 将与识别的晶片运行数相对应的半导体芯片的待机电流的测量值从数据库下载到半导体封装测试器; 通过使用半导体封装测试器提取定义下载的待机电流测量值的预定上限值的边界值; 将边界值设置为通过使用半导体封装测试器来测试半导体封装的程序的备用电流极限; 并根据待机电流限制测试半导体封装。

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