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1. 发明授权

US09324391B2 Dual event command 有权
标题翻译：双重事件命令
公开(公告)号：US09324391B2
公开(公告)日：2016-04-26
申请号：US12478270
申请日：2009-06-04
申请人： Joo S. Choi , Troy A. Manning , Brent Keeth
发明人： Joo S. Choi , Troy A. Manning , Brent Keeth
IPC分类号： G06F12/02 , G11C7/10 , G06F13/16
CPC分类号： G11C11/4076 , G06F12/0207 , G06F13/1668 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C11/408 , G11C11/409
摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
摘要翻译：一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

2. 发明授权

US07969814B2 Read command triggered synchronization circuitry 有权
标题翻译：读命令触发同步电路
公开(公告)号：US07969814B2
公开(公告)日：2011-06-28
申请号：US12544969
申请日：2009-08-20
申请人： Joo S. Choi
发明人： Joo S. Choi
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4096
摘要： A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off.
摘要翻译：存储器READ命令触发时钟同步模式仅对存储器读操作打开时钟同步电路。时钟同步电路在比列地址选通延迟更短的时间内实现了具有参考时钟信号的信号锁定。因此，当通过允许时钟同步电路被关闭而不执行这种操作时，精确存储器读操作就可能不浪费电力。

3. 发明申请

US20100265777A1 MEMORY DEVICE HAVING STROBE TERMINALS WITH MULTIPLE FUNCTIONS 有权
标题翻译：具有多个功能的结构终端的存储器件
公开(公告)号：US20100265777A1
公开(公告)日：2010-10-21
申请号：US12827954
申请日：2010-06-30
申请人： Joo S. Choi , Troy A. Manning
发明人： Joo S. Choi , Troy A. Manning
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1063 , G11C7/1066 , G11C7/1072 , G11C7/109 , G11C7/1093 , G11C2207/2254
摘要： A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of the output data. The memory device also has an auxiliary circuit for generating auxiliary information. The auxiliary information includes information different from the timing information of the input data and the output data. The auxiliary circuit uses the write and read transceivers to transfer the auxiliary information to and from the memory device.
摘要翻译：存储器件具有数据收发器，写选通收发器和读选通收发器。数据收发器将输入数据传输到存储器件并从存储器件传送输出数据。写入选通收发器传送输入数据的定时信息。读选通收发器传输输出数据的定时信息。存储装置还具有用于产生辅助信息的辅助电路。辅助信息包括与输入数据和输出数据的定时信息不同的信息。辅助电路使用写入和读取收发器将辅助信息传送到存储器件和从存储器件传送辅助信息。

4. 发明授权

US07817483B2 Memory device having terminals for transferring multiple types of data 有权
标题翻译：具有用于传送多种数据类型的终端的存储设备
公开(公告)号：US07817483B2
公开(公告)日：2010-10-19
申请号：US12326737
申请日：2008-12-02
申请人： Joo S. Choi
发明人： Joo S. Choi
IPC分类号： G11C7/10
CPC分类号： G11C7/1063 , G06F11/1032 , G11C5/066 , G11C7/04 , G11C7/1006 , G11C7/1048 , G11C7/1075 , G11C11/4096 , G11C29/022 , G11C29/028 , G11C2029/0409 , G11C2207/2254
摘要： A memory device includes terminals for transferring input data and output data to and from a memory array. The memory device also includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information and time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred.
摘要翻译：存储器件包括用于传送输入数据并向存储器阵列输出数据的端子。存储装置还包括辅助电路，用于接收与输入数据相关联的输入辅助信息，并用于产生与输出数据相关联的输出辅助信息。输入和输出辅助信息包括反转码，奇偶校验码，温度信息和时间延迟信息。输入和输出辅助信息在输入数据和输出数据传输的相同终端上传送到存储器件和从存储器件传送。

5. 发明授权

US07593287B2 READ command triggered synchronization circuitry 失效
标题翻译： READ命令触发同步电路
公开(公告)号：US07593287B2
公开(公告)日：2009-09-22
申请号：US12249689
申请日：2008-10-10
申请人： Joo S. Choi
发明人： Joo S. Choi
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4096
摘要： A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off.
摘要翻译：存储器READ命令触发时钟同步模式仅对存储器读操作打开时钟同步电路。时钟同步电路在比列地址选通延迟更短的时间内实现了具有参考时钟信号的信号锁定。因此，当通过允许时钟同步电路被关闭而不执行这种操作时，精确存储器读操作就可能不浪费电力。

6. 发明授权

US07245551B2 Read command triggered synchronization circuitry 有权
标题翻译：读命令触发同步电路
公开(公告)号：US07245551B2
公开(公告)日：2007-07-17
申请号：US10922429
申请日：2004-08-19
申请人： Joo S Choi
发明人： Joo S Choi
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4096
摘要： A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off.
摘要翻译：存储器READ命令触发时钟同步模式仅对存储器读操作打开时钟同步电路。时钟同步电路在比列地址选通延迟更短的时间内实现了具有参考时钟信号的信号锁定。因此，当通过允许时钟同步电路被关闭而不执行这种操作时，精确存储器读操作就可能不浪费电力。

7. 发明授权

US07116600B2 Memory device having terminals for transferring multiple types of data 有权
标题翻译：具有用于传送多种数据类型的终端的存储设备
公开(公告)号：US07116600B2
公开(公告)日：2006-10-03
申请号：US10782717
申请日：2004-02-19
申请人： Joo S. Choi
发明人： Joo S. Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/1063 , G06F11/1032 , G11C5/066 , G11C7/04 , G11C7/1006 , G11C7/1048 , G11C7/1075 , G11C11/4096 , G11C29/022 , G11C29/028 , G11C2029/0409 , G11C2207/2254
摘要： A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information or time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred.
摘要翻译：存储器件包括用于传送输入数据并向存储器阵列输出数据的多个端子。存储器件包括辅助电路，用于接收与输入数据相关联的输入辅助信息并产生与输出数据相关联的输出辅助信息。输入和输出辅助信息包括反转码，奇偶校验码，温度信息或时间延迟信息。输入和输出辅助信息在输入数据和输出数据传输的相同终端上传送到存储器件和从存储器件传送。

8. 发明授权

US06980480B2 Multi-frequency synchronizing clock signal generator 有权
公开(公告)号：US06980480B2
公开(公告)日：2005-12-27
申请号：US10835361
申请日：2004-04-28
申请人： Joo S. Choi
发明人： Joo S. Choi
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4076 , G11C8/00 , H03L7/00
CPC分类号： G11C29/028 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C29/50012
摘要： An apparatus and method for generating a plurality of synchronizing signals for synchronizing operation of the device in which the apparatus is located, such as in semiconductor memory devices. The apparatus can generate a plurality of synchronizing signals based on a corresponding plurality of input clock signals and select one of the synchronizing signals to be provided as the synchronizing clock signal. Alternatively, the apparatus can generate a plurality of internal clock signals based on an input clock signal, and generate a corresponding plurality of synchronizing signals from the plurality of internal clock signals. One of the synchronizing signals is selected by the apparatus as the synchronizing clock signal. Alternatively, the apparatus can receive a clock signal, generate a synchronized clock signal therefrom, and generate a synchronizing pulse in response to number of periods of the synchronized clock signal, the number based on a selection signal provided to the apparatus.

9. 发明授权

US06914852B2 Multi-frequency synchronizing clock signal generator 有权
标题翻译：多频同步时钟信号发生器
公开(公告)号：US06914852B2
公开(公告)日：2005-07-05
申请号：US10835360
申请日：2004-04-28
申请人： Joo S. Choi
发明人： Joo S. Choi
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4076 , G11C8/00
CPC分类号： G11C29/028 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C29/50012
摘要： An apparatus and method for generating a plurality of synchronizing signals for synchronizing operation of the device in which the apparatus is located, such as in semiconductor memory devices. The apparatus can generate a plurality of synchronizing signals based on a corresponding plurality of input clock signals and select one of the synchronizing signals to be provided as the synchronizing clock signal. Alternatively, the apparatus can generate a plurality of internal clock signals based on an input clock signal, and generate a corresponding plurality of synchronizing signals from the plurality of internal clock signals. One of the synchronizing signals is selected by the apparatus as the synchronizing clock signal. Alternatively, the apparatus can receive a clock signal, generate a synchronized clock signal therefrom, and generate a synchronizing pulse in response to number of periods of the synchronized clock signal, the number based on a selection signal provided to the apparatus.
摘要翻译：一种用于生成多个同步信号的装置和方法，用于使设备所处的装置的操作同步，诸如在半导体存储器件中。该装置可以基于相应的多个输入时钟信号产生多个同步信号，并选择要提供的同步信号之一作为同步时钟信号。或者，该装置可以基于输入时钟信号产生多个内部时钟信号，并且从多个内部时钟信号产生相应的多个同步信号。其中一个同步信号由装置选择为同步时钟信号。或者，该装置可以接收时钟信号，从其产生同步的时钟信号，并且响应于同步时钟信号的周期数，产生基于提供给该装置的选择信号的数量的同步脉冲。

10. 发明授权

US08295120B2 Read command triggered synchronization circuitry 失效
标题翻译：读命令触发同步电路
公开(公告)号：US08295120B2
公开(公告)日：2012-10-23
申请号：US13169587
申请日：2011-06-27
申请人： Joo S. Choi
发明人： Joo S. Choi
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4096
摘要： A system having a processor, a memory controller coupled to said processor, a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller and at least one of said DRAM chips comprising a clock synchronization circuit to receive a reference clock signal and to output a synchronized clock output signal. The system has a plurality of signal buses coupling the processor to the memory controller and the memory controller to said DRAM chips. The signal line conveys signals from said memory controller to said clock synchronization circuit to turn on and off the clock synchronization circuit according to control logic. A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off.
摘要翻译：一种具有处理器，耦合到所述处理器的存储器控制器，耦合到所述存储器控制器的多个动态随机存取存储器（DRAM）芯片和至少一个所述DRAM芯片的系统，所述DRAM芯片包括时钟同步电路以接收参考时钟信号和输出同步的时钟输出信号。该系统具有多个信号总线，该处理器将存储器控制器和存储器控制器耦合到所述DRAM芯片。信号线将来自所述存储器控制器的信号传送到所述时钟同步电路，以根据控制逻辑打开和关闭时钟同步电路。存储器READ命令触发时钟同步模式仅对存储器读操作打开时钟同步电路。时钟同步电路在比列地址选通延迟更短的时间内实现了具有参考时钟信号的信号锁定。因此，当通过允许时钟同步电路被关闭而不执行这种操作时，精确存储器读操作就可能不浪费电力。

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