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1. 发明申请

US20160043100A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20160043100A1
公开(公告)日：2016-02-11
申请号：US14668938
申请日：2015-03-25
申请人： Hyunmin LEE , CHANGSEOK KANG , JONGWON KIM , Hyeong PARK
发明人： Hyunmin LEE , CHANGSEOK KANG , JONGWON KIM , Hyeong PARK
IPC分类号： H01L27/115 , H01L23/535
CPC分类号： H01L27/11582 , H01L23/535 , H01L27/11565 , H01L2924/0002 , H01L2924/00
摘要： Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. The vertical channel structures penetrate the stack structure. Conductive pads are disposed on the vertical channel structures. An etch stopper covers sidewalls of the conductive pads. Pad contacts are disposed on the conductive pads to be in contact with the conductive pads. The pad contacts are further in contact with the etch stopper.
摘要翻译：本发明的概念提供半导体存储器件及其制造方法。堆叠结构和垂直通道结构设置在基板上。堆叠结构包括在基板上交替重复堆叠的绝缘层和栅电极。垂直通道结构穿透堆叠结构。导电垫设置在垂直通道结构上。蚀刻停止器覆盖导电焊盘的侧壁。焊盘触点设置在导电焊盘上以与导电焊盘接触。焊盘触点进一步与蚀刻停止器接触。

2. 发明授权

US06573476B2 Flux cored wire for gas-shielded arc welding 有权
标题翻译：用于气体保护电弧焊的焊剂芯焊丝
公开(公告)号：US06573476B2
公开(公告)日：2003-06-03
申请号：US09960369
申请日：2001-09-24
申请人： Jongwon Kim , Chulgyu Park
发明人： Jongwon Kim , Chulgyu Park
IPC分类号： B23K3534
CPC分类号： B23K35/368 , B23K35/3608
摘要： The flux cored wire comprises, with respect to the total weight of the wire, a Ti and a Ti oxide of 3.0 wt % to 8.0 wt % as calculated in terms of TiO2 content, a Si and a Si oxide of 0.5 wt % to 2.0 wt % as calculated in terms of SiO2 content, a metal Mn and an alloy of Mn of 1.5 wt % to 3.5 wt % as calculated in terms of Mn content, a carbon (C) of 0.02 wt % to 0.10 wt %, an Mg and an Mg oxide of 0.5 wt % to 1.5 wt % as calculated in terms of MgO content, a compound of Na2O and K2O of 0.2 wt % and less, a Zr and a Zr oxide of 0.1 wt % to 0.5 wt % as calculated in terms of ZrO2 content, and an Al and an Al oxide of 0.2 wt % to 0.8 wt % as calculated in terms of Al2O3 content.
摘要翻译：药芯焊丝相对于导线的总重量包含以TiO 2含量计算的3.0重量％至8.0重量％的Ti和Ti氧化物，0.5重量％至2.0重量％的Si和Si氧化物以Mn含量计算的Mn含量为1.5重量％〜3.5重量％的Mn的金属Mn和合金，碳量（C）为0.02重量％〜0.10重量％，Mg 和按MgO计算的0.5重量％〜1.5重量％的Mg氧化物，Na2O和K2O的化合物为0.2重量％以下，Zr和Zr氧化物为0.1重量％〜0.5重量％，计算公式如下：以ZrO 2含量计，以Al 2 O 3含量计算的Al和Al氧化物为0.2重量％〜0.8重量％。

3. 发明授权

US06414269B1 Pit and blow hole resistant flux-cored wire for gas-shielded arc welding of galvanized steel sheet 有权
公开(公告)号：US06414269B1
公开(公告)日：2002-07-02
申请号：US09791710
申请日：2001-02-26
申请人： Jongwon Kim
发明人： Jongwon Kim
IPC分类号： B23K3502
摘要： The present invention discloses a pit and blow hole resistant flux-cored wire for gas-shielded arc welding of a galvanized steel sheet. Here, an amount of flux ranges from 10 to 20% by weight of the wire, and an amount of a mild steel sheath ranges from 80 to 90% by weight of the wire. The flux comprising iron powder, deoxidizer and arc stabilizer in a residual amount is filled in the mild steel sheath. In detail, the flux contains a slag generation agent in an amount of 2 to 15% by weight of the wire, silicon oxide in an amount of 1.0 to 10 wt %, a component containing at least two components containing metal titanium, selected from the group consisting of metal titanium, metal magnesium and alloy mixtures thereof in an amount of 0.4 to 3 wt %, and one of sodium fluoride and potassium fluoride in an amount of 0.1 to 1 wt %. Accordingly, even when a plated layer is thick, it is possible to minimize generation of pits and blow holes in the welding. Moreover, generation of fumes and spatters can be controlled, which results in improved weldability. As a result, the pit and blow hole resistant flux-cored wire can be efficiently used for a consecutive or automated welding process.

4. 发明申请

US20160293626A1 SEMICONDUCTOR MEMORY DEVICES 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20160293626A1
公开(公告)日：2016-10-06
申请号：US15059993
申请日：2016-03-03
申请人： JONGWON KIM , HYEONG PARK , HYUNMIN LEE , HOJONG KANG , JOOWON PARK , SEUNGMIN SONG
发明人： JONGWON KIM , HYEONG PARK , HYUNMIN LEE , HOJONG KANG , JOOWON PARK , SEUNGMIN SONG
IPC分类号： H01L27/115 , H01L23/528 , H01L23/522
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11575
摘要： A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.
摘要翻译：半导体存储器件包括堆叠结构，其包括垂直堆叠在衬底上的栅电极和穿过栅电极的垂直沟道部分，连接到垂直沟道部分的位线和连接到堆叠上的栅电极的多条导线结构体。导线形成多个堆叠层，并且包括第一导线和第二导线。从衬底设置在第一电平的第一导电线的数量不同于从衬底设置在第二电平的第二导电线的数量。第一级与第二级不同。

5. 发明申请

US20100224962A1 INTEGRATED CIRCUIT RESISTIVE DEVICES INCLUDING MULTIPLE INTERCONNECTED RESISTANCE LAYERS 有权
标题翻译：集成电路电阻器件，包括多个互连电阻层
公开(公告)号：US20100224962A1
公开(公告)日：2010-09-09
申请号：US12699558
申请日：2010-02-03
申请人： Jongwon Kim
发明人： Jongwon Kim
IPC分类号： H01L27/06
CPC分类号： H01L27/101 , H01L23/5228 , H01L27/0802 , H01L27/11573 , H01L27/11578 , H01L27/11582 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate comprising a cell region and a peripheral circuit region, a first resistance layer and a second resistance layer spaced apart from each other and sequentially stacked on the semiconductor substrate of the peripheral circuit region, a first plug connected to the first resistance layer, and a second plug connected to the first and second resistance layers in common.
摘要翻译：半导体器件包括：半导体衬底，包括单元区域和外围电路区域;第一电阻层和第二电阻层，彼此间隔开并依次堆叠在外围电路区域的半导体衬底上;第一插头，第一电阻层和与第一和第二电阻层共同连接的第二插头。

6. 发明授权

US06476356B2 Metal cored wire for gas shielded arc welding having excellent zinc primer resistant performance and low temperature impact toughness 有权
公开(公告)号：US06476356B2
公开(公告)日：2002-11-05
申请号：US09842854
申请日：2001-04-27
申请人： Jongwon Kim
发明人： Jongwon Kim
IPC分类号： B23K3502
CPC分类号： B23K35/3608 , B23K35/3607 , B23K35/361 , B23K35/368
摘要： A flux cored wire for gas-shielded arc welding is disclosed. The flux cored wire is excellent in a zinc resistant primer performance and a low temperature impact toughness and comprises a flux filled in a mild steel sheath. The flux comprises: an oxide of TiO2+SiO2+Al2O3 in an amount of 2% to 10% by weight of the wire; at least one component in an amount of 0.1% to 1.0% by weight of the wire, the one component being selected from a metal fluoride group consisting of CaF2, NaF, K2SiF6, Na2SiF6 and KF, a metal titanium in an amount of 0.1% to 0.25 t % by weight of the wire; a metal boron in an amount of 0.002% to 0.008% by weight of the wire; and a subsidiary component in an amount of 5% to 20% by weight of the wire, the subsidiary component consisting of an iron component, a deoxidizer and an arc stabilizer.

7. 发明授权

US09246813B2 Flow control node for managing throughput fairness of a plurality of flows, transmission node, method for controlling flow, and method for controlling transmission rate 有权
标题翻译：用于管理多个流的吞吐量公平性的流控制节点，传输节点，用于控制流的方法以及用于控制传输速率的方法
公开(公告)号：US09246813B2
公开(公告)日：2016-01-26
申请号：US13703784
申请日：2011-10-21
申请人： Jongwon Kim , Jae-Yong Yoo
发明人： Jongwon Kim , Jae-Yong Yoo
IPC分类号： H04L12/26 , H04L12/801 , H04L12/835
CPC分类号： H04L47/10 , H04L47/11 , H04L47/30
摘要： According to one embodiment of the present invention, a multi-hop network system includes: a transmission node; a reception node; a router node; and a flow control node connected to all nodes within the multi-hop network system. The flow control node periodically receives flow monitoring information from at least one transmission node and evaluates whether the distributed state of the bandwidth of a network is fair. At this time, the flow control node sets a queue length threshold as transmission rate control information for fairly distributing the bandwidth of the network and transmits the set queue length threshold to at least one transmission node when unfairness has been detected. The transmission node sets the queue length threshold as a reference point for adjusting the transmission rate and performs the packet and/or link scheduling.
摘要翻译：根据本发明的一个实施例，多跳网络系统包括：传输节点; 接收节点; 路由器节点; 以及连接到多跳网络系统内的所有节点的流控制节点。流控制节点周期性地从至少一个传输节点接收流监视信息，并评估网络带宽的分布状态是否公平。此时，流量控制节点将队列长度阈值设置为用于公平分配网络带宽的传输速率控制信息，并且当检测到不公平时将设置的队列长度阈值发送到至少一个传输节点。发送节点将队列长度阈值设置为用于调整传输速率的参考点，并执行分组和/或链路调度。

8. 发明授权

US08996708B2 Method of providing content information using wireless communication device and navigation device performing the same 有权
标题翻译：使用无线通信设备和执行该内容信息的导航设备提供内容信息的方法
公开(公告)号：US08996708B2
公开(公告)日：2015-03-31
申请号：US13002364
申请日：2009-06-29
申请人： Jongwon Kim
发明人： Jongwon Kim
IPC分类号： G06F15/173 , G06F15/16 , G06F7/04 , H04B1/00 , H04M11/00 , H04W24/00 , H04B1/38 , G08G1/0967 , G01C21/36 , G08G1/0962 , H04W12/06 , H04W4/00 , H04M1/60 , H04M1/725 , H04W8/00 , H04W88/04 , H04W76/02 , H04L29/08
CPC分类号： G08G1/096775 , G01C21/3691 , G01C21/3697 , G08G1/0962 , G08G1/096716 , H04L67/12 , H04M1/6075 , H04M1/7253 , H04W4/80 , H04W8/005 , H04W12/06 , H04W76/14 , H04W88/04
摘要： A method of providing content information using a wireless communication device and a navigation device of performing the method are disclosed. The navigation device may comprise a terminal searching unit that searches a wireless communication terminal that may perform near field wireless communication in response to a content information providing request, a terminal authenticating unit that performs terminal authentication on whether the searched wireless communication terminal has been subscribing for a content providing service, and a content information displaying unit that, if it is identified that the wireless communication terminal is a terminal subscribing for the content providing service, receives content information from the wireless communication terminal and displays the content information on a display.
摘要翻译：公开了一种使用无线通信装置和执行该方法的导航装置提供内容信息的方法。导航装置可以包括：终端搜索单元，其搜索可以响应于内容信息提供请求执行近场无线通信的无线通信终端;终端认证单元，对所搜索的无线通信终端是否已经订阅内容提供服务，以及内容信息显示单元，如果识别出无线通信终端是订阅内容提供服务的终端，则从无线通信终端接收内容信息，并将该内容信息显示在显示器上。

9. 发明申请

US20120187503A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120187503A1
公开(公告)日：2012-07-26
申请号：US13427090
申请日：2012-03-22
申请人： JONGWON KIM
发明人： JONGWON KIM
IPC分类号： H01L27/088
CPC分类号： H01L21/28
摘要： Provided are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a semiconductor substrate including a first active region and a second active region, a gate electrode including a silicide layer formed on the first active region and a resistor pattern formed on the second active region. A distance from a top surface of the semiconductor substrate to a top surface of the resistor pattern is smaller than a distance from a top surface of the semiconductor substrate to a top surface of the gate electrode.
摘要翻译：提供半导体存储器件和半导体存储器件的制造方法。半导体存储器件包括包括第一有源区和第二有源区的半导体衬底，包括形成在第一有源区上的硅化物层的栅电极和形成在第二有源区上的电阻图案。从半导体衬底的顶表面到电阻器图案的顶表面的距离小于从半导体衬底的顶表面到栅电极的顶表面的距离。

10. 发明授权

US08227897B2 Integrated circuit resistive devices including multiple interconnected resistance layers 有权
标题翻译：集成电路电阻器件，包括多个互连的电阻层
公开(公告)号：US08227897B2
公开(公告)日：2012-07-24
申请号：US12699558
申请日：2010-02-03
申请人： Jongwon Kim
发明人： Jongwon Kim
IPC分类号： H01L29/00
CPC分类号： H01L27/101 , H01L23/5228 , H01L27/0802 , H01L27/11573 , H01L27/11578 , H01L27/11582 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate comprising a cell region and a peripheral circuit region, a first resistance layer and a second resistance layer spaced apart from each other and sequentially stacked on the semiconductor substrate of the peripheral circuit region, a first plug connected to the first resistance layer, and a second plug connected to the first and second resistance layers in common.
摘要翻译：半导体器件包括：半导体衬底，包括单元区域和外围电路区域;第一电阻层和第二电阻层，彼此间隔开并依次堆叠在外围电路区域的半导体衬底上;第一插头，第一电阻层和与第一和第二电阻层共同连接的第二插头。

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