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1. 发明授权

US06678569B2 User configurable multivariate time series reduction tool control method 有权
标题翻译：用户可配置的多变量时间序列减少工具控制方法
公开(公告)号：US06678569B2
公开(公告)日：2004-01-13
申请号：US10013070
申请日：2001-11-06
申请人： Raymond J. Bunkofske , John Z. Colt, Jr. , James J McGill , Nancy T. Pascoe , Maheswaran Surendra , Marc A. Taubenblatt , Asif Ghias
发明人： Raymond J. Bunkofske , John Z. Colt, Jr. , James J McGill , Nancy T. Pascoe , Maheswaran Surendra , Marc A. Taubenblatt , Asif Ghias
IPC分类号： G06F1900
CPC分类号： G05B23/0221 , G05B2219/45031 , H01L22/20
摘要： A method and structure for controlling a manufacturing tool includes measuring different manufacturing parameters of the tool, transforming a plurality of time series of the manufacturing parameters into intermediate variables based on restrictions and historical reference statistics, generating a surrogate variable based on the intermediate variables, if the surrogate variable exceeds a predetermined limit, identifying a first intermediate variable, of the intermediate variables, that caused the surrogate variable to exceed the predetermined limit and identifying a first manufacturing parameter associated with the first intermediate variable, and inhibiting further operation of the tool until the first manufacturing parameter has been modified to bring the surrogate value within the predetermined limit.
摘要翻译：用于控制制造工具的方法和结构包括测量工具的不同制造参数，基于限制和历史参考统计将多个制造参数的时间序列变换为中间变量，基于中间变量生成替代变量，如果替代变量超过预定的限制，识别导致替代变量超过预定极限的中间变量的第一中间变量，并且识别与第一中间变量相关联的第一制造参数，并且禁止工具的进一步操作直到修改了第一制造参数以使代理值在预定限度内。

2. 发明授权

US06383892B1 Double silicon-on-insulator device and method thereof 失效
标题翻译：双绝缘体硅器件及其方法
公开(公告)号：US06383892B1
公开(公告)日：2002-05-07
申请号：US09225315
申请日：1999-01-05
申请人： John Z. Colt, Jr.
发明人： John Z. Colt, Jr.
IPC分类号： H01L2130
CPC分类号： H01L21/7624
摘要： An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provides controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to create multiple vertically stacked isolated devices. Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation modes.
摘要翻译：一种集成电路芯片，其中一个或多个半导体器件与同一电路中的其它半导体器件的本体效应完全隔离，以及制造集成电路芯片的方法。这些器件可以是无源器件，例如电阻器或有源器件，例如二极管，双极晶体管或场效应晶体管（FET）。多层半导体体优选由硅和二氧化硅形成。在一个或多个层中形成导电区域或沟道。对于FET，沟道区上方和下方的硅提供具有垂直对称器件特性的可控制栅极。可以添加埋置的绝缘体层以将各个器件的下栅极彼此隔离并且产生多个垂直堆叠的隔离器件。 PFET和NFET器件都可以在耗尽和累积模式下以独立的掺杂分布形成。

3. 发明授权

US06584368B2 User configurable multivariate time series reduction tool control method 有权
公开(公告)号：US06584368B2
公开(公告)日：2003-06-24
申请号：US10245461
申请日：2002-09-17
申请人： Raymond J. Bunkofske , John Z. Colt, Jr. , James J. McGill , Nancy T. Pascoe , Maheswaran Surendra , Marc A. Taubenblatt , Asif Ghias
发明人： Raymond J. Bunkofske , John Z. Colt, Jr. , James J. McGill , Nancy T. Pascoe , Maheswaran Surendra , Marc A. Taubenblatt , Asif Ghias
IPC分类号： G05B1500
CPC分类号： G05B23/0221 , G05B2219/45031 , H01L22/20
摘要： A method and structure for controlling a manufacturing tool includes measuring different manufacturing parameters of the tool, transforming a plurality of time series of the manufacturing parameters into intermediate variables based on restrictions and historical reference statistics, generating a surrogate variable based on the intermediate variables, if the surrogate variable exceeds a predetermined limit, identifying a first intermediate variable, of the intermediate variables, that caused the surrogate variable to exceed the predetermined limit and identifying a first manufacturing parameter associated with the first intermediate variable, and inhibiting further operation of the tool until the first manufacturing parameter has been modified to bring the surrogate value within the predetermined limit.

4. 发明授权

US6013936A Double silicon-on-insulator device and method therefor 有权
标题翻译：双绝缘体硅器件及其方法
公开(公告)号：US6013936A
公开(公告)日：2000-01-11
申请号：US130299
申请日：1998-08-06
申请人： John Z. Colt, Jr.
发明人： John Z. Colt, Jr.
IPC分类号： H01L29/73 , H01L21/02 , H01L21/265 , H01L21/329 , H01L21/331 , H01L21/762 , H01L27/085 , H01L27/12 , H01L29/786 , H01L23/16 , H01L23/48
CPC分类号： H01L21/7624
摘要： An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provides controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to create multiple vertically stacked isolated devices. Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation modes.
摘要翻译：一种集成电路芯片，其中一个或多个半导体器件与同一电路中的其它半导体器件的本体效应完全隔离，以及制造集成电路芯片的方法。这些器件可以是无源器件，例如电阻器或有源器件，例如二极管，双极晶体管或场效应晶体管（FET）。多层半导体体优选由硅和二氧化硅形成。在一个或多个层中形成导电区域或沟道。对于FET，沟道区上方和下方的硅提供具有垂直对称器件特性的可控制栅极。可以添加埋置的绝缘体层以将各个器件的下栅极彼此隔离并且产生多个垂直堆叠的隔离器件。 PFET和NFET器件都可以在耗尽和累积模式下以独立的掺杂分布形成。

5. 发明授权

US07007855B1 Wafer identification mark 失效
公开(公告)号：US07007855B1
公开(公告)日：2006-03-07
申请号：US09527761
申请日：2000-03-17
申请人： Brian C. Barker , Raymond J. Bunkofske , John Z. Colt, Jr. , Perry G. Hartswick , John W. Lewis , Nancy T. Pascoe
发明人： Brian C. Barker , Raymond J. Bunkofske , John Z. Colt, Jr. , Perry G. Hartswick , John W. Lewis , Nancy T. Pascoe
IPC分类号： G06K19/06
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54413 , H01L2223/54433 , H01L2223/54453 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer including a plurality of pits in the semiconductor wafer. The pits are arranged in an information-providing pattern and are readable after completion of processing on the wafer.

6. 发明授权

US06442445B1 User configurable multivariate time series reduction tool control method 失效
公开(公告)号：US06442445B1
公开(公告)日：2002-08-27
申请号：US09272434
申请日：1999-03-19
申请人： Raymond J. Bunkofske , John Z. Colt, Jr. , James J. McGill , Nancy T. Pascoe , Maheswaran Surendra , Marc A. Taubenblatt , Asif Ghias
发明人： Raymond J. Bunkofske , John Z. Colt, Jr. , James J. McGill , Nancy T. Pascoe , Maheswaran Surendra , Marc A. Taubenblatt , Asif Ghias
IPC分类号： G06F1900
CPC分类号： G05B23/0221 , G05B2219/45031 , H01L22/20
摘要： A method and structure for controlling a manufacturing tool includes measuring different manufacturing parameters of the tool, transforming a plurality of time series of the manufacturing parameters into intermediate variables based on restrictions and historical reference statistics, generating a surrogate variable based on the intermediate variables, if the surrogate variable exceeds a predetermined limit, identifying a first intermediate variable, of the intermediate variables, that caused the surrogate variable to exceed the predetermined limit and identifying a first manufacturing parameter associated with the first intermediate variable, and inhibiting further operation of the tool until the first manufacturing parameter has been modified to bring the surrogate value within the predetermined limit.

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