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1. 发明授权

US6128026A Double buffered graphics and video accelerator having a write blocking memory interface and method of doing the same 失效
标题翻译：具有写阻塞存储器接口的双缓冲图形和视频加速器以及执行相同的方法
公开(公告)号：US6128026A
公开(公告)日：2000-10-03
申请号：US122422
申请日：1998-07-24
申请人： John W. Brothers, III
发明人： John W. Brothers, III
IPC分类号： G06T1/60 , G06F13/18 , G09G1/16 , G09G5/00 , G09G5/393 , G09G5/397 , G09G5/399 , G06F13/00
CPC分类号： G09G3/003 , G09G5/393 , G09G5/399 , G09G2340/02 , G09G5/001
摘要： A write blocking accelerator provides maximum concurrency between a central processing unit (CPU) and the accelerator by allowing writes to the front buffer of a dual-buffered system. The CPU issues a series of drawing commands followed by a "page flip" command. When a command parser within the accelerator receives a page flip command, it notifies a screen refresh unit reading from the front buffer that the command was received. The screen refresh unit signals a memory interface unit (MIU) to enter a write blocking mode and provides the address of the current line in the front buffer from which the screen refresh unit is reading, and the address of the last line in the front buffer. The MIU blocks all writes from drawing engines that fall into the range defined between the two addresses. The screen refresh sends updated front buffer addresses to the MIU as display data is read out of the front buffer. Accordingly, the blocked address range constantly shrinks until all writes are allowed by the MIU. At that point, the screen refresh unit signals the MIU that it has reached vertical retrace and the MIU exits write blocking mode.
摘要翻译：写阻塞加速器通过允许写入双缓冲系统的前缓冲区，在中央处理器（CPU）和加速器之间提供最大的并发性。 CPU发出一系列绘图命令，后跟“翻页”命令。当加速器内的命令解析器接收到页面翻转命令时，它通知屏幕刷新单元从前缓冲器读取该命令。屏幕刷新单元向存储器接口单元（MIU）发出信号以进入写入阻塞模式，并提供当前行在当前行中的屏幕刷新单元正在读取的地址，以及前面缓冲区中最后一行的地址。 MIU阻止来自绘图引擎的所有写入落入两个地址之间定义的范围内。屏幕刷新将更新的前缓冲区地址发送到MIU，因为显示数据从前缓冲区中读出。因此，阻塞的地址范围不断缩小，直到MIU允许所有写入。此时，屏幕刷新单元向MIU发出信号已经达到垂直回扫并且MIU退出写入阻塞模式。

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