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1. 发明申请

US20100118043A1 RECONFIGURABLE HIGH-PERFORMANCE TEXTURE PIPELINE WITH ADVANCED FILTERING 有权
标题翻译：可重复使用的高性能纹路管道，具有先进的过滤功能
公开(公告)号：US20100118043A1
公开(公告)日：2010-05-13
申请号：US12689939
申请日：2010-01-19
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J.M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J.M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
IPC分类号： G09G5/00
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。

2. 发明授权

US08031204B1 Font filter using bilinear interpolation 有权
标题翻译：使用双线性插值的字体过滤器
公开(公告)号：US08031204B1
公开(公告)日：2011-10-04
申请号：US11766741
申请日：2007-06-21
申请人： Paul S. Heckbert , John W. Berendsen
发明人： Paul S. Heckbert , John W. Berendsen
IPC分类号： G09G5/00
CPC分类号： G09G5/28 , G06T5/002 , G06T11/203
摘要： Systems and methods used for bilinear texture filtering may also be used to perform font filtering. Font data stored as a texture is read from memory in blocks that are coarsely aligned. Font alignment units may be used to provide a finely aligned region of the font data within a font filter footprint. The finely aligned region is then filtered using bilinear filtering to produce font coverage information representing a grayscale value for a pixel. Using existing bilinear filtering engines in conjunction with font alignment and sample units reduces the need for having a specific engine to perform each of the font filtering operations, possibly saving die area in a graphics system.
摘要翻译：用于双线性纹理过滤的系统和方法也可用于执行字体过滤。作为纹理存储的字体数据以粗略对齐的块从存储器读取。字体对齐单元可以用于在字体过滤器占用空间内提供字体数据的精细对准的区域。然后使用双线性滤波来过滤精细对准的区域，以产生表示像素的灰度值的字体覆盖信息。使用现有的双线性滤波引擎结合字体对齐和采样单元减少了对特定引擎执行每个字体过滤操作的需求，从而可能在图形系统中节省模具面积。

3. 发明授权

US07884831B2 Reconfigurable high-performance texture pipeline with advanced filtering 有权
标题翻译：可重构高性能纹理管道，具有先进的过滤功能
公开(公告)号：US07884831B2
公开(公告)日：2011-02-08
申请号：US12689939
申请日：2010-01-19
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
IPC分类号： G06T17/00 , G06T11/40 , G09G5/00 , G09G5/02 , G06K9/40 , G06K9/32 , G06K9/64
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。

4. 发明授权

US07522173B1 Conversion of data in an sRGB format to a compact floating point format 有权
标题翻译：将sRGB格式的数据转换为紧凑型浮点格式
公开(公告)号：US07522173B1
公开(公告)日：2009-04-21
申请号：US11360362
申请日：2006-02-23
申请人： John W. Berendsen
发明人： John W. Berendsen
IPC分类号： G09G5/02 , G09G5/00
CPC分类号： G09G5/02 , G09G2340/06
摘要： Systems and methods for processing linear colorspace data may be reused to process nonlinear colorspace data at a comparable performance level while maintaining the precision of the nonlinear colorspace data. Nonlinear colorspace data is converted to a compact floating point format in a linear colorspace used by conventional graphics processors. The compact floating point format includes an 8 bit explicit mantissa (without an implied leading one) and a 3 bit exponent to maintain the precision of the nonlinear colorspace data. The 8 bit mantissa may be processed by conventional texture filtering units designed to process 8 bit (fixed or floating point) color values. The 3 bit exponent may by processed by conventional texture filtering units designed to process floating point color values.
摘要翻译：用于处理线性颜色空间数据的系统和方法可以被重用以在可比较的性能水平处理非线性颜色空间数据，同时保持非线性颜色空间数据的精度。非线性色彩空间数据在传统图形处理器使用的线性色彩空间中转换为紧凑型浮点格式。紧凑型浮点格式包括8位显式尾数（无隐含前置码）和3位指数，以维持非线性色彩空间数据的精度。 8位尾数可以由旨在处理8位（固定或浮点）颜色值的常规纹理滤波单元进行处理。 3位指数可以通过设计用于处理浮点颜色值的常规纹理过滤单元进行处理。

5. 发明授权

US07490208B1 Architecture for compact multi-ported register file 有权
标题翻译：体积小巧的多端口寄存器文件
公开(公告)号：US07490208B1
公开(公告)日：2009-02-10
申请号：US10959560
申请日：2004-10-05
申请人： Lordson Yue , John W. Berendsen , Karim M. Abdalla , Rui M. Bastos , Radoslav Danilak
发明人： Lordson Yue , John W. Berendsen , Karim M. Abdalla , Rui M. Bastos , Radoslav Danilak
IPC分类号： G06F13/372 , G06F12/00
CPC分类号： G06F13/372
摘要： Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port for read operations and for write operations. Either a single read or a single write operation is performed for a given clock via the single port. Moreover, the single-port RAM serially performs N read operations and M write operations associated with a data group using a clock phase of (N+M) clock phases generated from a clock. In another embodiment, a semiconductor device includes the architecture for compact multi-ported register file. The semiconductor device comprises a plurality of register files. Each register file comprises a RAM comprising a port for read operations and for write operations. Moreover, each RAM serially performs N read operations and M write operations associated with one of a plurality of data groups using a corresponding clock phase of (N+M) clock phases generated from a clock. Further, the semiconductor device comprises an input staging unit for staging write data of one or more of the write operations. Continuing, the semiconductor device comprises an output staging unit for staging read data of one or more of the read operations. The semiconductor device can be a graphics processing unit (GPU).
摘要翻译：公开了用于紧凑型多端口寄存器堆的架构。在一个实施例中，寄存器文件包括单端口随机存取存储器（RAM）。单端口RAM包括用于读取操作和写入操作的单个端口。通过单个端口对给定的时钟执行单个读取或单个写入操作。此外，单端口RAM使用从时钟产生的（N + M）个时钟相位的时钟相位来串行地执行与数据组相关联的N个读取操作和M个写入操作。在另一个实施例中，半导体器件包括用于紧凑型多端口寄存器堆的结构。半导体器件包括多个寄存器文件。每个寄存器文件包括RAM，其包括用于读操作和写操作的端口。此外，每个RAM使用从时钟生成的（N + M）个时钟相位的相应时钟相位，串行地执行与多个数据组之一相关联的N个读取操作和M个写入操作。此外，半导体器件包括用于对一个或多个写入操作的写入数据进行分级的输入分段单元。继续地，半导体器件包括用于对读取操作中的一个或多个读取数据进行分级的输出分段单元。半导体器件可以是图形处理单元（GPU）。

6. 发明授权

US07649538B1 Reconfigurable high performance texture pipeline with advanced filtering 有权
标题翻译：可重构的高性能纹理管道与先进的过滤
公开(公告)号：US07649538B1
公开(公告)日：2010-01-19
申请号：US11556674
申请日：2006-11-03
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donovan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donovan , Emmett M. Kilgariff
IPC分类号： G06T17/00 , G06T11/40 , G09G5/00 , G09G5/02 , G06K9/40 , G06K9/32 , G06K9/64
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。

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