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1. 发明授权

US4087681A Asynchronous to synchronous converter 失效
标题翻译：异步到同步转换器
公开(公告)号：US4087681A
公开(公告)日：1978-05-02
申请号：US695290
申请日：1976-06-11
申请人： John Patrick Spencer , Anthony Joseph Torre
发明人： John Patrick Spencer , Anthony Joseph Torre
IPC分类号： G06K7/016 , G06K7/14
CPC分类号： G06K7/0166
摘要： An asynchronous to synchronous converter is disclosed which produces clock pulses in synchronism with data bits of a non-return-to-zero code having a variable data rate. The converter comprises a first bit clock generator which is adapted to produce a first timing signal for the first bit clock pulse of a data pulse which is one or more bits in width. The bit width is measured separately for high level and low level data pulses and the timing signal is generated accordingly. It also comprises a second bit clock generator which produces successive timing signals, one for each additional bit width, according to the maximum allowable number of bits per data pulse. Means are provided for compensating for systematic error in measured bit widths such as caused by ink spread variations. Additionally, means are provided to insert a bit clock pulse in the event of a missing pulse in the bit clock stream. Also, a digital noise rejection means is provided.
摘要翻译：公开了一种异步同步转换器，其产生与具有可变数据速率的非归零代码的数据位同步的时钟脉冲。转换器包括第一位时钟发生器，其适于产生宽度为一个或多个位的数据脉冲的第一位时钟脉冲的第一定时信号。为高电平和低电平数据脉冲单独测量位宽度，并相应地生成定时信号。它还包括第二位时钟发生器，其根据每个数据脉冲的最大允许位数产生连续的定时信号，每个附加位宽度一个。提供了用于补偿测量的位宽度（例如由油墨扩散变化引起的）的系统误差的装置。另外，提供了在位时钟流中缺少脉冲的情况下插入位时钟脉冲的装置。另外，提供数字噪声抑制装置。

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