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1. 发明授权

US06694382B1 Flexible I/O subsystem architecture and associated test capability 有权
标题翻译：灵活的I / O子系统架构和相关测试能力
公开(公告)号：US06694382B1
公开(公告)日：2004-02-17
申请号：US09643060
申请日：2000-08-21
申请人： Mark A. Kovalan , Bryon L. Wiscons , Ronald W. Aull , John L. Persick
发明人： Mark A. Kovalan , Bryon L. Wiscons , Ronald W. Aull , John L. Persick
IPC分类号： G06F300
CPC分类号： G05B19/0423 , G05B2219/21012 , G05B2219/23236
摘要： A data transfer mechanism for directing data signals from signal-producing elements to signal-receiving elements is disclosed. The data transfer mechanism includes a plurality of input ports, with each input port being connected to a signal-producing element, and a plurality of output ports, with each output port being connected to a signal-receiving element. Each data signal that enters the data transfer mechanism through one of the plurality of input ports has data identification information associated therewith. The, data transfer mechanism directs the data signal to at least one of the plurality of output ports according to the data identification information associated with the data signal.
摘要翻译：公开了一种用于将数据信号从信号产生元件引导到信号接收元件的数据传送机构。数据传送机构包括多个输入端口，每个输入端口连接到信号产生元件，以及多个输出端口，每个输出端口连接到信号接收元件。通过多个输入端口之一进入数据传送机制的每个数据信号具有与其相关联的数据识别信息。数据传输机构根据与数据信号相关联的数据识别信息将数据信号引导到多个输出端口中的至少一个。

2. 发明授权

US06453374B1 Data bus 失效
标题翻译：数据总线
公开(公告)号：US06453374B1
公开(公告)日：2002-09-17
申请号：US09281584
申请日：1999-03-30
申请人： Mark A. Kovalan , Bryon L. Wiscons , John L. Persick , Douglas R. Johnson , Gregory E. Dunn , Stephen I. Kotalik
发明人： Mark A. Kovalan , Bryon L. Wiscons , John L. Persick , Douglas R. Johnson , Gregory E. Dunn , Stephen I. Kotalik
IPC分类号： G06F1300
CPC分类号： G06F13/4286
摘要： A bus system including a bus user apparatus and a method for communicating via the bus system are disclosed. The bus user apparatus includes means for means for selectively coupling a transmitter to the transmission line according to a protocol of the bus system. The bus system provides bi-directional communication over a single transmission line. The transmitter of the transmitting device is coupled to the transmission line during transmission. Upon completion of transmission, the transmitting device sends a permission to transmit signal to the next transmitting device according to the protocol, and decouples its transmitter from the transmission line. The next transmitting device couples its transmitter to the transmission line and begins transmission of data. Multiple bus users, both transmitters and receivers, are accommodated by the bus system, and bi-directional communication is supported. Further, the data transmission rate may be increased by selectively coupling the transmitter of a receiving device to the transmission line to provide a termination impedance on the transmission line. Higher transmission rates may be accommodated without a termination impedance; if necessary, a termination impedance may be applied. If necessary, the output voltage of the transmitter and the sensitivity of the receiver may be adjusted to accommodate the higher transmission rates. The bus system may also accommodate larger sized words. The bus system is compatible with previously existing systems compliant with an ARINC standard while providing increased capability.
摘要翻译：公开了一种包括总线用户装置和通过总线系统进行通信的方法的总线系统。总线用户装置包括用于根据总线系统的协议选择性地将发射机耦合到传输线的装置的装置。总线系统通过单个传输线提供双向通信。发射装置的发射机在传输期间耦合到传输线路。传输完成后，发送设备根据协议向下一个发送设备发送发送信号的许可，并将其发射机与传输线路分离。下一个发送设备将其发射机耦合到传输线并开始传输数据。多个总线用户（发送器和接收器）都由总线系统容纳，并支持双向通信。此外，可以通过选择性地将接收装置的发射机耦合到传输线来提供传输线上的终端阻抗来增加数据传输速率。可以容纳更高的传输速率而没有终端阻抗; 如果需要，可以施加终止阻抗。如果需要，可以调整发射机的输出电压和接收机的灵敏度以适应较高的传输速率。总线系统还可以容纳较大尺寸的字。总线系统与先前存在的符合ARINC标准的系统兼容，同时提供增强的功能。

3. 发明授权

US07852235B1 High integrity computing via input synchronization systems and methods 有权
标题翻译：通过输入同步系统和方法实现高完整性计算
公开(公告)号：US07852235B1
公开(公告)日：2010-12-14
申请号：US12150402
申请日：2008-04-28
申请人： Douglas R. Johnson , James J. Corcoran , Eric J. Danielson , John W. Roltgen , Mark A. Kovalan , Corydon J. Carlson , John L. Persick , Cleveland C. Gilbert , Samir S. Hemaidan , Shawn M. Stanger
发明人： Douglas R. Johnson , James J. Corcoran , Eric J. Danielson , John W. Roltgen , Mark A. Kovalan , Corydon J. Carlson , John L. Persick , Cleveland C. Gilbert , Samir S. Hemaidan , Shawn M. Stanger
IPC分类号： G08B21/00 , G08B29/00 , G06F11/00 , G01C23/00
CPC分类号： G06F11/1641 , G06F11/1637 , G06F11/1687
摘要： A method of comparing output information from dissimilar processors includes storing a task in a first memory and storing the task in a second memory at substantially the same time as the first memory. The time of the storing being is controlled by a first arbitration logic and a second arbitration logic. The method also includes receiving the task by a first processor from the first memory and receiving the task by a second processor from the memory at substantially the same time as the first processor. The time being received is controlled by a first arbitration logic and a second arbitration logic. The second processor being dissimilar to the first processor. The method further includes computing a first output by the first processor based on the task and computing a second output by the second processor based on the task. The method still further includes, synchronizing the first and second outputs so that the first and second outputs are output at substantially the same time. The synchronizing is controlled by the first and second arbitration logic.
摘要翻译：比较来自不同处理器的输出信息的方法包括将任务存储在第一存储器中，并将该任务与第一存储器基本上同时存储在第二存储器中。存储的时间由第一仲裁逻辑和第二仲裁逻辑控制。该方法还包括由第一处理器从第一存储器接收任务，并且在与第一处理器基本相同的时间，由第二处理器从存储器接收任务。所接收的时间由第一仲裁逻辑和第二仲裁逻辑控制。第二处理器与第一处理器不相似。该方法还包括基于该任务计算第一处理器的第一输出并基于该任务计算第二处理器的第二输出。该方法还包括：使第一和第二输出同步，使得第一和第二输出基本上同时输出。同步由第一和第二仲裁逻辑控制。

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