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1. 发明授权

US5862128A Merged buffer signal switch 失效
公开(公告)号：US5862128A
公开(公告)日：1999-01-19
申请号：US580804
申请日：1995-12-29
申请人： Michael Cooperman , Nee-Ben Gee , John Edmund Rathke
发明人： Michael Cooperman , Nee-Ben Gee , John Edmund Rathke
IPC分类号： H04Q11/04 , H04J3/14
CPC分类号： H04L47/10 , H04L45/302 , H04L47/11 , H04L47/2441 , H04L47/263 , H04L47/29 , H04L47/32 , H04L49/3009 , H04Q11/0478 , H04J2203/001 , H04J2203/0012 , H04J2203/0019 , H04L49/101 , H04L49/3027 , H04L49/555
摘要： A signal switch with merged buffer architecture has multiple input ports connected to a circuit switch matrix which partially sorts the input signals based on output port destination. The circuit switch matrix is connected to multiple merged buffers, each in turn connected to a corresponding output port and feedback. Input signals entering the circuit switch matrix are normally sent to the buffer attached to the destination output port of the input signal, but, if more than one input signal is contending for an output port, all but the first contending input signal are misrouted to merged buffers that are not busy. The location in memory of all of the correctly routed and misrouted input signals in the switch is tracked by a control, which also routes input signals to their output port destinations from the merged buffers, and reroutes misrouted input signals to the correct buffers. The control does not reroute a misrouted signal until its intended buffer is no longer busy, so that each input signal is rerouted at most once. The control can also track the priority, sequence number, and output port destination of each input signal, in order to give preference to the higher priority input signals going to a particular output port. Buffer overflow can be minimized and switch resources more efficiently utilized by denying rerouted input signals access to a output buffer until the number of cells potentially waiting in that output buffer has dropped below a predetermined threshold. Buffer usage is balanced across the switch by changing the order in which buffers receive misrouted input signals. At the onset of congestion, signals are discarded when necessary at predetermined priority-dependent buffer signal occupancy thresholds. Multicasting can be handled by initially treating a multicast signal as a misrouted signal. The multicast signal is first routed to a merged buffer which did not receive a correctly routed signal, then it is rerouted simultaneously to all of the merged buffers corresponding to its output port destinations, so that all signals can be then sent to the appropriate output ports during a subsequent time period.

2. 发明授权

US5813040A Write controller for a CAM-based switch with lineraly searchable memory utilizing hardware-encoded status tags to indicate avaliablity of each memory location for writing 失效
标题翻译：使用基于硬件编码状态标签的线性搜索存储器的基于CAM的交换机的写控制器，以指示每个存储器位置的写入可用性
公开(公告)号：US5813040A
公开(公告)日：1998-09-22
申请号：US581742
申请日：1995-12-29
申请人： John Edmund Rathke
发明人： John Edmund Rathke
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0893
摘要： A write controller for a signal switch with a linearly searchable memory eliminates the need to maintain an ordered list of free addresses. The write controller utilizes a hardware encoded bit map and search logic to search linearly for memory locations that do not contain valid data and can therefore be written to. The search stops at the first memory location where the bit map tag indicates that the memory location is available, and then the write control logic unit associated with that memory location sends a kill signal that tells downstream write control logic units associated with other memory locations to deactivate. The write controller writes the data into the selected memory location and flips the status bit of that location to indicate that the memory location is no longer available for writing. The write controller then releases the restraining kill signal, allowing the next available memory location in line to receive data during the next clock cycle. The status bit for the memory location that was just written to continues to indicate that the memory location is not available for writing to until either the data is read out of the memory location or the system is reset. The memory location can during this time be read, but not written to. When a read of the location subsequently occurs in response to a read signal, the internal status bit is then flipped again so that the memory location will again be available to receive data.
摘要翻译：用于具有线性可搜索存储器的信号开关的写控制器消除了维护空闲地址的有序列表的需要。写控制器利用硬件编码位图和搜索逻辑来线性搜索不包含有效数据的存储器位置，因此可以被写入。搜索在位映射标签指示存储器位置可用的第一存储器位置停止，然后与该存储器位置相关联的写入控制逻辑单元发送杀死信号，其将与其它存储器位置相关联的下游写入控制逻辑单元告知停用。写控制器将数据写入所选存储单元，并翻转该位置的状态位，以指示存储器位置不再可用于写入。写控制器然后释放限制消除信号，允许下一个可用的存储器位置在下一个时钟周期内接收数据。正在写入的存储器位置的状态位继续表示存储器位置不可用于写入，直到数据从存储器位置读出或系统复位为止。内存位置可以在这段时间内被读取，但不能写入。当响应于读取信号而发生位置的读取时，再次翻转内部状态位，使得存储器位置将再次可用于接收数据。

3. 发明授权

US5774463A Switching matrix with contention arbitration 失效
标题翻译：具有争用仲裁的交换矩阵
公开(公告)号：US5774463A
公开(公告)日：1998-06-30
申请号：US581722
申请日：1995-12-29
申请人： Michael Cooperman , Nee-Ben Gee , John Edmund Rathke
发明人： Michael Cooperman , Nee-Ben Gee , John Edmund Rathke
IPC分类号： H04Q11/04 , H04L12/50
CPC分类号： H04Q11/0407 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13104 , H04Q2213/13166 , H04Q2213/1332
摘要： A switching matrix routes each received input to a unique output port. Each input specifies an output port as a destination. For each output port, a set of inputs contending for the output port is determined. A control for correctly routing selects an input from each set of contending inputs and routes it to the correct output port of the switching matrix. If no input specifies an output port as a destination, that output port is designated as an available output port. A control for misrouting determines the set of available output ports and the set of inputs that have not been correctly routed by the control for correctly routing. The control for misrouting then misroutes each remaining input to one of the available output ports of the switching matrix. The switching matrix may provide status signals for use by the switch in tracking the location of the correctly routed and misrouted inputs.
摘要翻译：开关矩阵将每个接收的输入路由到唯一的输出端口。每个输入都将输出端口指定为目的地。对于每个输出端口，确定与输出端口竞争的一组输入。用于正确路由的控制选择来自每组竞争输入的输入，并将其引导到交换矩阵的正确输出端口。如果没有输入指定输出端口作为目的地，该输出端口被指定为可用的输出端口。用于错误路由的控制决定了可用输出端口的集合以及由控制器未正确路由的正确路由选择的一组输入。然后对错误路由的控制错误地将每个剩余输入路由到交换矩阵的一个可用输出端口。开关矩阵可以提供状态信号，以供开关在跟踪正确路由和错误输入的输入的位置时使用。

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