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1. 发明授权

US09230725B2 Methods of designing an inductor having opening enclosed within conductive line 有权
标题翻译：设计具有封闭在导线内的开口的电感器的方法
公开(公告)号：US09230725B2
公开(公告)日：2016-01-05
申请号：US13404485
申请日：2012-02-24
申请人： Mete Erturk , John D. Gillis , Casey J. Grant , David Scagnelli , Anthony K. Stamper
发明人： Mete Erturk , John D. Gillis , Casey J. Grant , David Scagnelli , Anthony K. Stamper
IPC分类号： H01F17/06 , H01F41/04 , H01F17/00 , H01L23/522 , H01L23/528 , H01L23/64 , H01L49/02 , H01F17/04 , H01F27/28
CPC分类号： H01F17/0006 , H01F17/04 , H01F27/2847 , H01F41/04 , H01F41/041 , H01F41/045 , H01F2017/0053 , H01F2017/0073 , H01F2017/046 , H01L23/5227 , H01L23/528 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , Y10T29/49004 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073 , Y10T29/49156 , H01L2924/00
摘要： Embodiments are provided that include methods of designing an inductor. The inductor can include a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line. Embodiments of forming the inductor can include: providing an inductor design including a conductive line having at least one turn; determining a region of the conductive line that has current density below a threshold; and forming an opening in the region, the opening enclosed within the conductive line.
摘要翻译：提供了包括设计电感器的方法的实施例。电感器可以包括包括至少一个匝的导电线和位于导电线的区域的内部内的开口。形成电感器的实施例可以包括：提供包括具有至少一匝的导线的电感器设计; 确定电流密度低于阈值的导线的区域; 以及在该区域中形成开口，封闭在导电线内的开口。

2. 发明授权

US08193893B2 Inductor having opening enclosed within conductive line and related method 有权
标题翻译：具有封闭在导线内的开关的电感器和相关方法
公开(公告)号：US08193893B2
公开(公告)日：2012-06-05
申请号：US12055336
申请日：2008-03-26
申请人： Mete Erturk , John D. Gillis , Casey J. Grant , David Scagnelli , Anthony K. Stamper
发明人： Mete Erturk , John D. Gillis , Casey J. Grant , David Scagnelli , Anthony K. Stamper
IPC分类号： H01F5/00 , H01F27/28
CPC分类号： H01F17/0006 , H01F17/04 , H01F27/2847 , H01F41/04 , H01F41/041 , H01F41/045 , H01F2017/0053 , H01F2017/0073 , H01F2017/046 , H01L23/5227 , H01L23/528 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , Y10T29/49004 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073 , Y10T29/49156 , H01L2924/00
摘要： Embodiments of an inductor including a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line are disclosed. Embodiments of a related method of designing the inductor are also disclosed.
摘要翻译：公开了一种电感器的实施例，其包括包括至少一个匝的导线和位于导线的区域内部的开口。还公开了设计电感器的相关方法的实施例。

3. 发明申请

US20090243778A1 INDUCTOR HAVING OPENING ENCLOSED WITHIN CONDUCTIVE LINE AND RELATED METHOD 有权
标题翻译：具有导电线中开放的电感器及相关方法
公开(公告)号：US20090243778A1
公开(公告)日：2009-10-01
申请号：US12055336
申请日：2008-03-26
申请人： Mete Erturk , John D. Gillis , Casey J. Grant , David Scagnelli , Anthony K. Stamper
发明人： Mete Erturk , John D. Gillis , Casey J. Grant , David Scagnelli , Anthony K. Stamper
IPC分类号： H01F5/00 , G06F17/50
CPC分类号： H01F17/0006 , H01F17/04 , H01F27/2847 , H01F41/04 , H01F41/041 , H01F41/045 , H01F2017/0053 , H01F2017/0073 , H01F2017/046 , H01L23/5227 , H01L23/528 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , Y10T29/49004 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073 , Y10T29/49156 , H01L2924/00
摘要： Embodiments of an inductor including a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line are disclosed. Embodiments of a related method of designing the inductor are also disclosed.
摘要翻译：公开了一种电感器的实施例，其包括包括至少一个匝的导线和位于导线的区域内部的开口。还公开了设计电感器的相关方法的实施例。

4. 发明申请

US20120151748A1 METHODS OF DESIGNING AN INDUCTOR HAVING OPENING ENCLOSED WITHIN CONDUCTIVE LINE 有权
标题翻译：设计在导线中封闭的电感器的方法
公开(公告)号：US20120151748A1
公开(公告)日：2012-06-21
申请号：US13404485
申请日：2012-02-24
申请人： Mete Erturk , John D. Gillis , Casey J. Grant , David Scagnelli , Anthony K. Stamper
发明人： Mete Erturk , John D. Gillis , Casey J. Grant , David Scagnelli , Anthony K. Stamper
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： H01F17/0006 , H01F17/04 , H01F27/2847 , H01F41/04 , H01F41/041 , H01F41/045 , H01F2017/0053 , H01F2017/0073 , H01F2017/046 , H01L23/5227 , H01L23/528 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , Y10T29/49004 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073 , Y10T29/49156 , H01L2924/00
摘要： Embodiments disclosed include methods of designing an inductor. The inductor can include a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line.
摘要翻译：公开的实施例包括设计电感器的方法。电感器可以包括包括至少一个匝的导电线和位于导电线的区域的内部内的开口。

5. 发明授权

US08169055B2 Chip guard ring including a through-substrate via 有权
标题翻译：芯片保护环包括贯通基板通孔
公开(公告)号：US08169055B2
公开(公告)日：2012-05-01
申请号：US12634726
申请日：2009-12-10
申请人： John D. Gillis , Wan Ni
发明人： John D. Gillis , Wan Ni
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5225 , H01L23/585 , H01L29/78 , H01L2924/0002 , H01L2924/12044 , H01L2924/00012 , H01L2924/00
摘要： At least one through-substrate via is formed around the periphery of a semiconductor chip or a semiconductor chiplet included in a semiconductor chip. The at least one through-substrate via may be a single through-substrate via that laterally surrounds the semiconductor chip or the semiconductor chiplet, or may comprise a plurality of through-substrate vias that surrounds the periphery with at least one gap among the through-substrate vias. A stack of back-end-of-line (BEOL) metal structures that laterally surrounds the semiconductor chip or the semiconductor chiplet are formed directly on the substrate contact vias and electrically connected to the at least one through-substrate via. A metallic layer is formed on the backside of the semiconductor substrate including the at least one through-substrate via. The conductive structure including the metallic layer, the at least one through-substrate via, and the stack of the BEOL metal structures function as an electrical ground built into the semiconductor chip.
摘要翻译：至少一个贯通基板通孔形成在半导体芯片的周围或包含在半导体芯片中的半导体芯片周围。所述至少一个贯通基板通孔可以是横向围绕半导体芯片或半导体小芯片的单个贯穿基板通孔，或者可以包括多个贯穿基板通孔，其围绕周边具有贯通基板通孔中的至少一个间隙，衬底通孔。横向围绕半导体芯片或半导体小芯片的后端行（BEOL）金属结构的堆叠直接形成在基板接触通孔上并电连接到至少一个贯通基板通孔。在包括至少一个贯通基板通孔的半导体基板的背面上形成金属层。包括金属层的导电结构，至少一个贯通基板通孔以及BEOL金属结构的堆叠用作内置于半导体芯片中的电接地。

6. 发明申请

US20100237472A1 Chip Guard Ring Including a Through-Substrate Via 有权
标题翻译：芯片保护环包括通过基板通孔
公开(公告)号：US20100237472A1
公开(公告)日：2010-09-23
申请号：US12634726
申请日：2009-12-10
申请人： John D. Gillis , Wan Ni
发明人： John D. Gillis , Wan Ni
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5225 , H01L23/585 , H01L29/78 , H01L2924/0002 , H01L2924/12044 , H01L2924/00012 , H01L2924/00
摘要： At least one through-substrate via is formed around the periphery of a semiconductor chip or a semiconductor chiplet included in a semiconductor chip. The at least one through-substrate via may be a single through-substrate via that laterally surrounds the semiconductor chip or the semiconductor chiplet, or may comprise a plurality of through-substrate vias that surrounds the periphery with at least one gap among the through-substrate vias. A stack of back-end-of-line (BEOL) metal structures that laterally surrounds the semiconductor chip or the semiconductor chiplet are formed directly on the substrate contact vias and electrically connected to the at least one through-substrate via. A metallic layer is formed on the backside of the semiconductor substrate including the at least one through-substrate via. The conductive structure including the metallic layer, the at least one through-substrate via, and the stack of the BEOL metal structures function as an electrical ground built into the semiconductor chip.
摘要翻译：至少一个贯通基板通孔形成在半导体芯片的周围或包含在半导体芯片中的半导体芯片周围。所述至少一个贯通基板通孔可以是横向围绕半导体芯片或半导体小芯片的单个贯穿基板通孔，或者可以包括多个贯穿基板通孔，其围绕周边具有贯通基板通孔中的至少一个间隙，衬底通孔。横向围绕半导体芯片或半导体小芯片的后端行（BEOL）金属结构的堆叠直接形成在基板接触通孔上并电连接到至少一个贯通基板通孔。在包括至少一个贯通基板通孔的半导体基板的背面上形成金属层。包括金属层的导电结构，至少一个贯通基板通孔以及BEOL金属结构的堆叠用作内置于半导体芯片中的电接地。

7. 发明授权

US06711392B1 Balanced power amplifier for low power radio communications 有权
标题翻译：用于低功率无线电通信的平衡功率放大器
公开(公告)号：US06711392B1
公开(公告)日：2004-03-23
申请号：US09609066
申请日：2000-06-30
申请人： John D. Gillis
发明人： John D. Gillis
IPC分类号： H04B700
CPC分类号： H03G3/3042 , H03F1/02 , H03F3/24 , H03F3/602 , H03F3/72 , H03F2203/7206 , H03F2203/7215 , H03F2203/7221 , H04B1/406 , H04B2001/045
摘要： A balanced power amplifier for radio frequencies. The power amplifier may be switched from operating in a saturation mode, so that AMPS-type radio telephone signals may be optimally amplified, to a linear mode so that CDMA signals may be amplified. A directional coupler splits an input signal into quadrature signal components which are supplied to the input of a pair of dual mode power amplifiers. The output signals from the dual mode amplifiers are recombined in a directional coupler. The directional coupler effectively applies all of the output power to an antenna connected to one of the coupler ports, and effectively isolates the output stages of the amplifiers from any reflected power generated by the antenna.
摘要翻译：用于无线电频率的平衡功率放大器。功率放大器可以在饱和模式下工作，使得AMPS型无线电话信号可以被最佳地放大到线性模式，使得CDMA信号可以被放大。定向耦合器将输入信号分离成正交信号分量，其被提供给一对双模功率放大器的输入。来自双模放大器的输出信号在定向耦合器中重新组合。定向耦合器有效地将所有输出功率应用于连接到耦合器端口之一的天线，并且有效地将放大器的输出级与由天线产生的任何反射功率隔离开来。

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