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    • 1. 发明授权
    • System and method for multi-mode operation of satellite phased-array antenna
    • 卫星相控阵天线多模操作系统及方法
    • US06307507B1
    • 2001-10-23
    • US09519915
    • 2000-03-07
    • Joel Lloyd GrossJonathan Henry GrossRobert Anthony PetersDaniel Francis DiFonzo
    • Joel Lloyd GrossJonathan Henry GrossRobert Anthony PetersDaniel Francis DiFonzo
    • H01Q326
    • H01Q1/288H01Q3/2605H01Q25/002
    • A method and apparatus are provided for operating a phased-array antenna (14) on a satellite-based communications node (10) in more than one mode by controlling the number of beam-forming elements and by applying appropriate phase-control and/or amplitude-control coefficients to the selected elements. The antenna can be operated as a diffused-beam antenna at a relatively low data rate, enabling the satellite-communications node (10) to communicate with a first terrestrial communications node (22). The antenna can also be operated to generate multiple focused-beam antenna patterns each communicating at a relatively high data rate, enabling the satellite-communications node (10) to communicate with a different terrestrial communications node (20) by changing the amplitude and/or the phase coefficients as well as the number of beam-forming elements.
    • 提供了一种方法和装置,用于通过控制波束形成元件的数量并且通过施加适当的相位控制和/或多个方式来以多于一种模式在基于卫星的通信节点(10)上操作相控阵天线(14) 对所选元素的幅度控制系数。 天线可以以相对低的数据速率作为漫射波束天线来操作,使卫星通信节点(10)能够与第一地面通信节点(22)通信。 天线也可以被操作以产生多个以相对高的数据速率通信的聚焦波束天线方向图,使得卫星通信节点(10)可以通过改变振幅和/或波段来与不同的地面通信节点(20)通信 相位系数以及波束形成元件的数量。
    • 3. 发明授权
    • Apparatus and method for synchronizing a clock using a phase-locked loop circuit
    • 使用锁相环电路来同步时钟的装置和方法
    • US06633621B1
    • 2003-10-14
    • US09531689
    • 2000-03-20
    • Daniel Eric BishopGeorge Jeffrey GeierJeffrey Scott MoffettGeorge Arthur SchauerRoger Charles HartJoel Lloyd Gross
    • Daniel Eric BishopGeorge Jeffrey GeierJeffrey Scott MoffettGeorge Arthur SchauerRoger Charles HartJoel Lloyd Gross
    • H03D324
    • G04G7/00H03L7/087H03L7/093
    • A system for synchronizing a clock includes a phase-locked loop (PLL) circuit that generates or receives (304) timing errors that are based on timing information from multiple timing sources. Gain blocks (214) weight (306) the timing errors, which are then combined (308) into a loop time error. A loop integrator (226) integrates (310) the loop time error to produce an input used to adjust (312) an oscillator frequency. A corresponding oscillator clock signal is fed back (240) to one or more phase detectors (206), which receive (302) timing reference signals and generate timing errors. When a timing errors indicates that a problem exists with a timing source, the impact of the problematic timing source is reduced (430, 504), or oscillator frequency adjustments are suspended (608). When used on a satellite (700), at least one of the timing errors can be based on times of transmit and times of arrival of time messages exchanged between the satellite and its neighbors (716).
    • 用于同步时钟的系统包括基于来自多个定时源的定时信息生成或接收( 304 )定时误差的锁相环(PLL)电路。 ( 214 )权重( 306 )定时错误,然后组合( 308 )转换为循环时间错误。 循环积分器( 226 )将循环时间误差积分( 310 )以产生用于调整的输入( 312 )振荡器频率。 将相应的振荡器时钟信号反馈( 240 )到一个或多个相位检测器( 206 ), 302 )定时参考信号并产生定时误差。 当定时错误表示定时源存在问题时,减少了有问题的定时源的影响( 430,504 ),或者振荡器频率调整被暂停(< HIL> 608 )。 当在卫星( 700 )上使用时,定时错误中的至少一个可以基于在卫星与其邻居之间交换的时间消息的发送时间和到达时间 ( 716 )。
    • 5. 发明授权
    • Apparatus and method for maximizing transmit power output
    • 用于最大化发射功率输出的装置和方法
    • US6035181A
    • 2000-03-07
    • US963318
    • 1997-11-03
    • Joel Lloyd Gross
    • Joel Lloyd Gross
    • H03G3/30A61B1/04
    • H03G3/3042
    • An apparatus (10) and method (100) optimize the transmit output power of a power amplifier (14) while providing for controlled backoff independent of temperature, gain stackup or other common error effects. The apparatus (10) and method (100) are particularly relevant to single channel per carrier (SCPC) satellite transmissions, such as a K-band satellite transmissions. The apparatus (10) and method (100) provide the ability to set a maximum drive level of a power amplifier (14) using a feedback loop without overdriving the power amplifier (14) into compression. This approach controls the spectral regrowth that results from running the power amplifier (14) in saturation and limits the AM/PM conversion in the power amplifier (14).
    • 设备(10)和方法(100)优化功率放大器(14)的发射输出功率,同时提供独立于温度,增益叠加或其他常见误差效应的可控退避。 装置(10)和方法(100)与诸如K波段卫星传输的单载波(SCPC)卫星传输特别相关。 装置(10)和方法(100)提供使用反馈回路设置功率放大器(14)的最大驱动电平而不使功率放大器(14)过压驱动的能力。 该方法控制由饱和功率放大器(14)运行而产生的频谱再生长,并限制功率放大器(14)中的AM / PM转换。
    • 6. 发明授权
    • Demodulator with baseband doppler shift compensation and method
    • 具有基带多普勒频移补偿和方法的解调器
    • US5696797A
    • 1997-12-09
    • US279376
    • 1994-07-22
    • William Alexander BucherMark Alan KirschenmannJoel Lloyd GrossClay Garlen Jones
    • William Alexander BucherMark Alan KirschenmannJoel Lloyd GrossClay Garlen Jones
    • H04L27/00H04L27/233H04L27/06
    • H04L27/2332H04L2027/003H04L2027/0057H04L2027/0095
    • An apparatus and accompanying method for demodulating with baseband Doppler frequency shift compensation. An RF section (20) down-converts received data communication signals (12) to baseband. A/D converters (24, 26) digitize I, Q quadrature baseband signal components. Phase (32) and frequency (50) tracking loops reside on a common digital ASIC substrate (28). A complex multiplier (30) rotates digitized baseband signals by a digitized oscillation signal, producing Doppler shift compensated signals. The phase tracking loop (32) estimates data and generates a pure phase error signal from which data modulation and Doppler shift compensation influences have been removed, which drives a frequency discriminator (52) that identifies either clockwise or counterclockwise phase rotation for each symbol (18). An integrator (54) combines identification results over a burst and a numerically controlled oscillator (56) adjusts the digitized oscillation signal frequency in a constant frequency step. This adjustment takes place once for each burst.
    • 一种用基带多普勒频移补偿进行解调的装置及其附带方法。 RF部分(20)将接收的数据通信信号(12)下变频到基带。 A / D转换器(24,26)数字化I,Q正交基带信号分量。 相位(32)和频率(50)跟踪环路驻留在公共数字ASIC基板(28)上。 复数乘法器(30)通过数字化的振荡信号旋转数字化的基带信号,产生多普勒频移补偿信号。 相位跟踪环路(32)估计数据并产生一个纯相位误差信号,数据调制和多普勒频移补偿影响已从该相位误差信号中消除,驱动一个频率鉴别器(52),它识别每个符号(18)的顺时针或逆时针相位旋转 )。 积分器(54)将突发的识别结果与数控振荡器(56)组合,以恒定频率步长调整数字化的振荡信号频率。 对于每个突发,这种调整发生一次。