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    • 2. 发明授权
    • Method and circuitry for generating r-bit parallel CRC code for an l-bit
data source
    • 用于为1位数据源生成r位并行CRC码的方法和电路
    • US5671238A
    • 1997-09-23
    • US550574
    • 1995-10-31
    • Kim-Joan ChenChing-Long Chang
    • Kim-Joan ChenChing-Long Chang
    • H03M13/09H03M13/29H03M13/00
    • H03M13/091H03M13/29
    • A method for generating r-bit parallel CRC code for a data source grouped into at least one successive p-bit parallel data group and a q-bit parallel data group is disclosed. The number q is less than the number p. The method includes the steps of: providing a data processing unit which has an output side and an input side that is adapted to receive successively the p-bit and q-bit parallel data groups, the processing unit reflecting one of the p-bit parallel data groups at the input side to the output side when the p-bit parallel data group is present at the input side, the processing unit adding a bit string to the q-bit parallel data group such that sum of the number q and number of bits in the bit string is equal to the number p, the processing unit presenting the q-bit parallel data group and the bit string at the output side when the q-bit parallel data group is present at the input side; providing a binary output generating unit which operates in response to data at the output side to produce an r-bit parallel initial CRC code according to a predefined generating polynomial function; and providing a code correcting unit which receives the r-bit parallel initial CRC code from the generating unit and which operates in response to the parallel initial CRC code to produce an r-bit parallel final CRC code according to a predefined code correcting function.
    • 公开了一种用于为分组成至少一个连续的p位并行数据组和q位并行数据组的数据源产生r位并行CRC码的方法。 数字q小于数字p。 该方法包括以下步骤:提供一个数据处理单元,该数据处理单元具有适于连续接收p位和q位并行数据组的输出侧和输入端,该处理单元反映p位并行 当在输入侧存在p位并行数据组时,在输出侧的输入侧的数据组,处理单元向q位并行数据组添加位串,使得数字q和数量的和 比特串中的比特数等于数字p,当q比特并行数据组存在于输入侧时,表示q比特并行数据组的处理单元和输出侧的比特串; 提供二进制输出生成单元,其响应于输出侧的数据进行操作,以根据预定义的生成多项式函数产生r位并行初始CRC码; 并提供代码校正单元,其从所述生成单元接收所述r位并行初始CRC码,并且响应于所述并行初始CRC码操作以根据预定义的代码校正功能产生r位并行最终CRC码。