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1. 发明授权

US08988510B2 3D image display device 有权
标题翻译： 3D图像显示设备
公开(公告)号：US08988510B2
公开(公告)日：2015-03-24
申请号：US12879709
申请日：2010-09-10
申请人： Byungsam Min , Kiduk Kim , Sunhwa Lee , Jinwoo Hong
发明人： Byungsam Min , Kiduk Kim , Sunhwa Lee , Jinwoo Hong
IPC分类号： H04N13/04 , G02B27/22 , G09G3/00 , G09G3/36 , G09G3/34
CPC分类号： G02B27/2264 , G09G3/003 , G09G3/3406 , G09G3/3666 , G09G2320/064 , H04N13/341 , H04N13/398
摘要： A three-dimensional (3D) image display device includes a liquid crystal display panel alternately displaying a left eye image and a right eye image every unit frame period, a data driving circuit, a gate driving circuit, a timing controller that divides the unit frame period into first and second sub-frame periods, repeatedly supply the same frame data to the data driving circuit during the first and second sub-frame periods, and control operations of the data and gate driving circuits using a frame frequency higher than an input frame frequency, backlight light sources generating light to be provided to the liquid crystal display panel, and a light source driving circuit that sequentially turns on the backlight light sources when liquid crystals of the liquid crystal display panel are kept in a saturation state.
摘要翻译：三维（3D）图像显示装置包括每单位帧周期交替显示左眼图像和右眼图像的液晶显示面板，数据驱动电路，门驱动电路，定时控制器，其将单位框架在第一和第二子帧周期内重复地向数据驱动电路提供相同的帧数据，以及使用高于输入帧的帧频的数据和门驱动电路的控制操作产生要提供给液晶显示面板的光的背光光源，以及当液晶显示面板的液晶保持在饱和状态时顺序打开背光光源的光源驱动电路。

2. 发明授权

US08664707B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08664707B2
公开(公告)日：2014-03-04
申请号：US13428706
申请日：2012-03-23
申请人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
发明人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L21/8221 , H01L27/0688 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.
摘要翻译：提供了一种半导体器件，其可以包括在衬底上的下互连和布置在下互连上的至少一个上互连。至少一个栅极结构可以设置在上部互连和下部互连之间，其中栅极结构可以包括垂直堆叠的多条栅极线，使得每个栅极线具有基本上平行于上部的布线部分所述基板的表面和从所述布线部沿着穿过所述基板的上表面的方向延伸的接触部。至少一个半导体图案可以连接上部和下部互连。

3. 发明申请

US20140015032A1 INTEGRATED CIRCUIT MEMORY DEVICES HAVING VERTICAL TRANSISTOR ARRAYS THEREIN AND METHODS OF FORMING SAME 有权
标题翻译：具有垂直晶体管阵列的集成电路存储器件及其形成方法
公开(公告)号：US20140015032A1
公开(公告)日：2014-01-16
申请号：US14024737
申请日：2013-09-12
申请人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
发明人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.
摘要翻译：集成电路器件包括其中具有可独立控制的栅电极的垂直堆叠的晶体管阵列。提供第一半导体沟道区，其在独立可控栅电极的垂直叠层的第一侧壁上延伸。还提供了第一电绝缘层，其在第一半导体沟道区域和独立可控栅电极的垂直叠层的第一侧壁之间延伸。源极和漏极区分别电耦合到第一半导体沟道区的第一和第二端。

4. 发明授权

US08541832B2 Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same 有权
公开(公告)号：US08541832B2
公开(公告)日：2013-09-24
申请号：US12816771
申请日：2010-06-16
申请人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
发明人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.

5. 发明申请

US20120275609A1 MULTI-OBJECT AUDIO ENCODING AND DECODING METHOD AND APPARATUS THEREOF 审中-公开
标题翻译：多对象音频编码和解码方法及其设备
公开(公告)号：US20120275609A1
公开(公告)日：2012-11-01
申请号：US13546358
申请日：2012-07-11
申请人： Seungkwon BEACK , Jeong-Il SEO , Kyeongok KANG , Jinwoo HONG , Jinwoong KIM , Taejin LEE
发明人： Seungkwon BEACK , Jeong-Il SEO , Kyeongok KANG , Jinwoo HONG , Jinwoong KIM , Taejin LEE
IPC分类号： H04R5/00
CPC分类号： G10L19/008
摘要： Provided are a multi-object audio encoding and decoding method and an apparatus thereof. The multi-object encoding method includes generating a down-mix signal and a residual signal by down-mixing a foreground audio object and a background audio object, and generating a bitstream including the down-mix signal and the residual signal.
摘要翻译：提供了一种多对象音频编码和解码方法及其装置。多对象编码方法包括通过对前景音频对象和背景音频对象进行下混合生成下混合信号和残留信号，并且生成包含缩混混合信号和残留信号的比特流。

6. 发明授权

US08164134B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08164134B2
公开(公告)日：2012-04-24
申请号：US12481403
申请日：2009-06-09
申请人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
发明人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
IPC分类号： H01L29/792 , H01L27/108
CPC分类号： H01L27/11578 , H01L21/8221 , H01L27/0688 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed.
摘要翻译：提供半导体器件及其制造方法。在衬底上形成限定至少一个第一开口的至少一个模具结构，其中模具结构包括顺序地和交替地堆叠的第一模具图案和第二模具图案。此后，选择性地蚀刻第一模具图案的侧表面以在第二模具图案之间形成底切区域。然后，形成半导体层以覆盖形成底切区域的模具结构的表面，形成栅极图案，填充形成半导体层的各个底切区域。

7. 发明授权

US07433314B2 Method and system for acknowledging the receipt of a transmitted data stream in a wireless personal area network 有权
标题翻译：用于确认在无线个人区域网络中接收到发送的数据流的方法和系统
公开(公告)号：US07433314B2
公开(公告)日：2008-10-07
申请号：US10928067
申请日：2004-08-27
申请人： Sanjeev K. Sharma , Jinwoo Hong
发明人： Sanjeev K. Sharma , Jinwoo Hong
IPC分类号： H04J3/24
CPC分类号： H04L1/1614 , H04L1/0083 , H04L1/1671 , H04W28/06 , H04W84/10 , H04W84/12
摘要： A method and system for acknowledging the receipt of a transmitted data stream in a wireless personal area network (WPAN) are disclosed. In one embodiment, a plurality of medium access control (MAC) protocol data units (MPDUs) are transmitted from a transmitting party to a receiving party, and the receiving entity sends a delayed acknowledgment frame to the transmitting party using a bitmap field for each of the fragmented packets instead of using two bytes of an MPDU block for acknowledging each received MPDU. The bitmap field includes a plurality of bitmap values corresponding to the plurality of MPDUs, and each of the plurality of bitmap values is indicative of whether each of the MPDUs is received or not.
摘要翻译：公开了一种在无线个域网（WPAN）中确认接收到发送数据流的方法和系统。在一个实施例中，多个介质访问控制（MAC）协议数据单元（MPDU）从发送方发送到接收方，并且接收实体使用位图字段向发送方发送延迟的确认帧，分段分组，而不是使用两个字节的MPDU块来确认每个接收到的MPDU。位图字段包括与多个MPDU对应的多个位图值，多个位图值中的每一个表示是否接收到每个MPDU。

8. 发明申请

US20110150098A1 APPARATUS AND METHOD FOR PROCESSING 3D AUDIO SIGNAL BASED ON HRTF, AND HIGHLY REALISTIC MULTIMEDIA PLAYING SYSTEM USING THE SAME 审中-公开
标题翻译：基于HRTF处理3D音频信号的装置和方法，以及使用该方法的高真实多媒体播放系统
公开(公告)号：US20110150098A1
公开(公告)日：2011-06-23
申请号：US12809458
申请日：2008-09-26
申请人： Yongju Lee , Inseon Jang , Daeyoung Jang , Jeong-Il Seo , Kyeongok Kang , Jinwoong Kim , Jinwoo Hong
发明人： Yongju Lee , Inseon Jang , Daeyoung Jang , Jeong-Il Seo , Kyeongok Kang , Jinwoong Kim , Jinwoo Hong
IPC分类号： H04N7/26 , H04R5/00
CPC分类号： H04S1/005 , G11B20/10 , G11B2020/10546 , H04R5/04 , H04R2499/11 , H04S1/002 , H04S2420/01
摘要： A three-dimensional audio signal processing apparatus using a Head Related Transfer Function (HRTF) includes an audio decoder for decoding audio data to restore original audio signals and a three-dimensional audio generator for generating three-dimensional signals corresponding to the audio signals restored by using the HRTF modeled according to physical characteristics of an user, wherein the HRTF modeled according to physical characteristics of an user is an individualized HRTF.
摘要翻译：使用头相关传送功能（HRTF）的三维音频信号处理装置包括用于对音频数据进行解码以恢复原始音频信号的音频解码器，以及三维音频发生器，用于产生对应于由使用根据用户的物理特征建模的HRTF，其中根据用户的物理特征建模的HRTF是个体化的HRTF。

9. 发明申请

US20110149047A1 3D IMAGE DISPLAY DEVICE 有权
标题翻译： 3D图像显示设备
公开(公告)号：US20110149047A1
公开(公告)日：2011-06-23
申请号：US12879709
申请日：2010-09-10
申请人： Byungsam Min , Kiduk Kim , Sunhwa Lee , Jinwoo Hong
发明人： Byungsam Min , Kiduk Kim , Sunhwa Lee , Jinwoo Hong
IPC分类号： H04N13/04
CPC分类号： G02B27/2264 , G09G3/003 , G09G3/3406 , G09G3/3666 , G09G2320/064 , H04N13/341 , H04N13/398
摘要： A three-dimensional (3D) image display device includes a liquid crystal display panel alternately displaying a left eye image and a right eye image every unit frame period, a data driving circuit, a gate driving circuit, a timing controller that divides the unit frame period into first and second sub-frame periods, repeatedly supply the same frame data to the data driving circuit during the first and second sub-frame periods, and control operations of the data and gate driving circuits using a frame frequency higher than an input frame frequency, backlight light sources generating light to be provided to the liquid crystal display panel, and a light source driving circuit that sequentially turns on the backlight light sources when liquid crystals of the liquid crystal display panel are kept in a saturation state.
摘要翻译：三维（3D）图像显示装置包括每单位帧周期交替显示左眼图像和右眼图像的液晶显示面板，数据驱动电路，门驱动电路，定时控制器，其将单位框架在第一和第二子帧周期内重复地向数据驱动电路提供相同的帧数据，以及使用高于输入帧的帧频的数据和门驱动电路的控制操作产生要提供给液晶显示面板的光的背光光源，以及当液晶显示面板的液晶保持在饱和状态时顺序打开背光光源的光源驱动电路。

10. 发明申请

US20110018051A1 Integrated Circuit Memory Devices Having Vertical Transistor Arrays Therein and Methods of Forming Same 有权
标题翻译：具有垂直晶体管阵列的集成电路存储器件及其形成方法相同
公开(公告)号：US20110018051A1
公开(公告)日：2011-01-27
申请号：US12816771
申请日：2010-06-16
申请人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
发明人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
IPC分类号： H01L27/115
CPC分类号： H01L29/7926 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.
摘要翻译：集成电路器件包括其中具有可独立控制的栅电极的垂直堆叠的晶体管阵列。提供第一半导体沟道区，其在独立可控栅电极的垂直叠层的第一侧壁上延伸。还提供了第一电绝缘层，其在第一半导体沟道区域和独立可控栅电极的垂直叠层的第一侧壁之间延伸。源极和漏极区分别电耦合到第一半导体沟道区的第一和第二端。

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